专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08667377B1 Circuit and method for parallel decoding 有权
标题翻译：电路和并行解码方法
公开(公告)号：US08667377B1
公开(公告)日：2014-03-04
申请号：US13228385
申请日：2011-09-08
申请人： Raied N. Mazahreh , Hai-Jo Tarn
发明人： Raied N. Mazahreh , Hai-Jo Tarn
IPC分类号： H03M13/00
CPC分类号： H03M13/1515 , H03M13/152 , H03M13/1545 , H03M13/2721 , H03M13/2906 , H03M13/2921 , H03M13/6561
摘要： In one embodiment, a block code decoder is provided. The block code decoder includes a first decoder configured to decode Bose-Chaudhuri-Hochquenghem (“BCH”) coded data packets and a second decoder configured to receive and decode Reed-Solomon (“RS”) encoded data from the first decoder. The first decoder includes a first buffer configured to receive BCH encoded data and one or more BCH decoder circuits coupled to the first buffer. Each BCH decoder circuit decodes a plurality of BCH encoded bits in parallel. A second buffer is arranged to store the decoded BCH data. The second decoder includes a third buffer, arranged to receive the RS encoded data from the first decoder, one or more RS decoder circuits configured to decode a plurality of RS encoded bits in parallel, and a fourth buffer arranged to store RS payload data decoded by the RS decoder circuits.
摘要翻译：在一个实施例中，提供了块码解码器。块码解码器包括：第一解码器，被配置为解码Bose-Chaudhuri-Hochquenghem（“BCH”）编码数据分组，以及第二解码器，被配置为从第一解码器接收和解码Reed-Solomon（“RS”）编码数据。第一解码器包括被配置为接收BCH编码数据的第一缓冲器和耦合到第一缓冲器的一个或多个BCH解码器电路。每个BCH解码器电路并行地解码多个BCH编码比特。第二缓冲器被布置成存储解码的BCH数据。第二解码器包括第三缓冲器，被配置为从第一解码器接收RS编码数据，一个或多个RS解码器电路，被配置为并行地解码多个RS编码比特;以及第四缓冲器，其被布置为存储由 RS解码电路。

2. 发明授权

US08416841B1 Multiple-input multiple-output (MIMO) decoding with subcarrier grouping 有权
标题翻译：具有子载波分组的多输入多输出（MIMO）解码
公开(公告)号：US08416841B1
公开(公告)日：2013-04-09
申请号：US12623624
申请日：2009-11-23
申请人： Hai-Jo Tarn , Raied N. Mazahreh , Raghavendar M. Rao
发明人： Hai-Jo Tarn , Raied N. Mazahreh , Raghavendar M. Rao
IPC分类号： H04B3/46
CPC分类号： H04L25/03891 , H04B7/0413 , H04L5/0023 , H04L25/03159 , H04L2025/03426
摘要： Multiple input multiple output (MIMO) receiver circuitry is described. In one circuit, input circuitry provides a matrix of unresolved symbols received from a plurality of receive antennas. Channel estimation circuitry constructs a plurality of channel matrices including at least two channel matrices corresponding first and second subcarriers, respectively. A preprocessing circuit receives input from the plurality of channel matrices and interleaves retrieved input into an input matrix. A first systolic array includes boundary cells and internal cells. The boundary cells and internal cells are configured to perform triangulation and back-substitution on the input matrix to produce an output matrix. A second systolic array performs right and left multiplication operations and cross-diagonal transpose on the output matrix to produce a weighted matrix. An output circuit multiplies the weighted matrix by the matrix of unresolved symbols from the input circuitry to produce an estimate of isolated symbols corresponding to the unresolved symbols.
摘要翻译：描述了多输入多输出（MIMO）接收机电路。在一个电路中，输入电路提供从多个接收天线接收的未解决符号的矩阵。信道估计电路分别构成包括对应于第一和第二子载波的至少两个信道矩阵的多个信道矩阵。预处理电路接收来自多个信道矩阵的输入并将检索的输入交织到输入矩阵中。第一个收缩阵列包括边界细胞和内部细胞。边界单元和内部单元被配置为在输入矩阵上执行三角测量和反替换以产生输出矩阵。第二收缩阵列在输出矩阵上执行右和左乘法运算和交叉对角线转置以产生加权矩阵。输出电路将加权矩阵乘以来自输入电路的未解析符号的矩阵，以产生对应于未解决符号的孤立符号的估计。

3. 发明授权

US07669017B1 Method of and circuit for buffering data 有权
标题翻译：缓冲数据的方法和电路
公开(公告)号：US07669017B1
公开(公告)日：2010-02-23
申请号：US11527802
申请日：2006-09-27
申请人： Hemang Maheshkumar Parekh , Hai-Jo Tarn , Gabor Szedo , Vanessa Yu-Mei Chou , Jeffrey Allan Graham , Elizabeth R. Cowie
发明人： Hemang Maheshkumar Parekh , Hai-Jo Tarn , Gabor Szedo , Vanessa Yu-Mei Chou , Jeffrey Allan Graham , Elizabeth R. Cowie
IPC分类号： G06F12/00
CPC分类号： H04L27/263 , G06F5/16 , G06F17/142
摘要： A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.
摘要翻译：描述了以自然地址顺序和修改的地址顺序在电路处理数据中缓冲数据的方法。该方法包括以下步骤：根据自然地址顺序或修改的地址顺序的第一寻址顺序存储第一数据块; 根据自然地址顺序和修改的地址顺序的另一寻址顺序读取存储在缓冲器中的第一数据块; 并且在按照另一个寻址顺序读取存储在缓冲器中的第一数据块时，以另一寻址顺序同时将第二数据块写入缓冲器。

4. 发明授权

US08875001B1 Circuitry for parallel decoding of data blocks 有权
标题翻译：数据块并行解码电路
公开(公告)号：US08875001B1
公开(公告)日：2014-10-28
申请号：US13228406
申请日：2011-09-08
申请人： Raied N. Mazahreh , Hai-Jo Tarn
发明人： Raied N. Mazahreh , Hai-Jo Tarn
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/1545 , H03M13/151 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/157 , H03M13/1575 , H03M13/2909 , H03M13/6561
摘要： In one embodiment, a Chien search circuit includes a plurality of evaluation circuits, each configured to sequentially evaluate possible roots αi in a respective subset of possible roots of an error location polynomial (Λ(x)). Each evaluation circuit includes a respective sub-circuit for each of a plurality of coefficients λi (0≦i≦T) of the error location polynomial Λ(x) having T+1 coefficients. Each sub-circuit is configured to calculate one term of the error location polynomial for each possible root αi in the respective subset of possible roots. Each evaluation circuit is configured to evaluate the error location polynomial for each possible root in the respective subset of possible roots, as a sum of the terms calculated by the plurality of sub-circuits.
摘要翻译：在一个实施例中，Chien搜索电路包括多个评估电路，每个评估电路被配置为依次评估错误位置多项式（Λ（x））的可能根的各个子集中的可能根αi。每个评估电路包括用于具有T + 1个系数的误差位置多项式Λ（x）的多个系数λi（0＆nlE; i＆nlE; T）中的每一个的相应子电路。每个子电路被配置为针对可能根的各个子集中的每个可能的根αi计算误差位置多项式的一项。每个评估电路被配置为评估可能根的相应子集中的每个可能根的误差位置多项式，作为由多个子电路计算的项的和。

5. 发明授权

US08620984B2 Minimum mean square error processing 有权
公开(公告)号：US08620984B2
公开(公告)日：2013-12-31
申请号：US12623656
申请日：2009-11-23
申请人： Raied N. Mazahreh , Hai-Jo Tarn , Raghavendar M. Rao
发明人： Raied N. Mazahreh , Hai-Jo Tarn , Raghavendar M. Rao
IPC分类号： G06F7/32 , G06F17/10
CPC分类号： G06F17/16 , G06F7/78 , G06F15/8046 , H04B7/0413 , H04B7/0854 , H04L25/0244
摘要： A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

6. 发明授权

US08001171B1 Pipeline FFT architecture for a programmable device 有权
标题翻译：可编程器件的管道FFT架构
公开(公告)号：US08001171B1
公开(公告)日：2011-08-16
申请号：US11445066
申请日：2006-05-31
申请人： James M. Simkins , Vasisht Mantra Vadi , Helen Hai-Jo Tarn
发明人： James M. Simkins , Vasisht Mantra Vadi , Helen Hai-Jo Tarn
IPC分类号： G06F15/00
CPC分类号： G06F17/142
摘要： A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one Least Significant Bit of the first output. A delay and swap stage is coupled to receive the first output and configured to provide a second output. A second Radix-2 butterfly stage is coupled to receive the second output and a second input, configured to provide a third output responsive thereto, and configured to truncate at least one Most Significant Bit of the third output. The first Radix-2 butterfly stage and the second Radix-2 butterfly stage are implemented in digital signal processing slices of a programmable device.
摘要翻译：描述了用于可编程设备的管线快速傅里叶变换（“FFT”）架构。第一基数2蝴蝶级被耦合以接收第一输入，被配置为响应于此提供第一输出，并且被配置为截断第一输出的至少一个最低有效位。耦合延迟和交换级以接收第一输出并且被配置为提供第二输出。第二基数2蝶形级耦合以接收第二输出和第二输入，第二输入被配置为响应于此提供第三输出，并且被配置为截断第三输出的至少一个最高有效位。第一个Radix-2蝴蝶舞台和第二个Radix-2蝴蝶舞台在可编程设备的数字信号处理片段中实现。

7. 发明申请

US20130254639A1 PARALLEL ENCODING FOR NON-BINARY LINEAR BLOCK CODE 有权
标题翻译：并行编码非二进制线性块代码
公开(公告)号：US20130254639A1
公开(公告)日：2013-09-26
申请号：US13430222
申请日：2012-03-26
申请人： Kalyana Krishnan , Hai-Jo Tarn
发明人： Kalyana Krishnan , Hai-Jo Tarn
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/13 , H03M13/05 , H03M13/1134 , H03M13/1137 , H03M13/1171 , H03M13/134 , H03M13/1515 , H03M13/21 , H03M13/6502 , H03M13/6561
摘要： An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.
摘要翻译：编码器模块包括顺序耦合的P / L奇偶校验移位寄存器，其中奇偶校验移位寄存器的第一奇偶移位寄存器的输入耦合到编码器模块的输入端，奇偶校验位的最后奇偶移位寄存器的输出移位寄存器耦合到编码器模块的输出，每个奇偶移位寄存器被配置为存储L个奇偶校验位。编码器模块还包括一个包括P / L奇偶校验生成模块的反馈电路，其中奇偶校验生成模块中的每一个通过开关耦合到奇偶移位寄存器中对应的一个的输出，并且还耦合到第一奇偶校验的输入移位寄存器，其中每个奇偶校验生成模块被配置为当其对应的开关闭合时，产生用于传输到第一奇偶移位寄存器的输入的L个奇偶校验位。

8. 发明授权

US07610453B1 Reordering each array in a sequence of arrays 有权
标题翻译：以数组的顺序重新排列每个数组
公开(公告)号：US07610453B1
公开(公告)日：2009-10-27
申请号：US11527883
申请日：2006-09-27
申请人： Hemang Maheshkumar Parekh , Jeffrey Allan Graham , Hai-Jo Tarn , Elizabeth R. Cowie , Vanessa Yi-Mei Chou
发明人： Hemang Maheshkumar Parekh , Jeffrey Allan Graham , Hai-Jo Tarn , Elizabeth R. Cowie , Vanessa Yi-Mei Chou
IPC分类号： G06F12/00
CPC分类号： G06F7/785
摘要： Each array in a sequence of arrays is reordered. A first port receives in a first serial order a number of values in each array in the sequence and a second port transmits the values in a different second serial order. For each value in each array in the sequence, the address generator generates an address within a range of zero through one less than the number of values in the array. For each address from the generator, the memory performs an access to a location corresponding to the address in the memory. The access for each address includes a read from the location before a write to the location. For each array in the sequence, the writes for the addresses serially write the values of the array in the first serial order and the reads for the addresses serially read the values in the second serial order.
摘要翻译：一系列数组中的每个数组被重新排序。第一端口以第一串行顺序接收序列中每个阵列中的多个值，并且第二端口以不同的第二串行顺序发送值。对于序列中每个数组中的每个值，地址生成器将生成一个范围从零到小于数组中数值的地址。对于来自发生器的每个地址，存储器执行对与存储器中的地址相对应的位置的访问。每个地址的访问包括从写入位置之前的位置读取。对于序列中的每个数组，地址的写入以第一个串行顺序串行写入数组的值，并且地址的读取以串行顺序读取第二个串行顺序的值。

9. 发明授权

US08949703B2 Parallel encoding for non-binary linear block code 有权
标题翻译：非二进制线性块代码的并行编码
公开(公告)号：US08949703B2
公开(公告)日：2015-02-03
申请号：US13430222
申请日：2012-03-26
申请人： Kalyana Krishnan , Hai-Jo Tarn
发明人： Kalyana Krishnan , Hai-Jo Tarn
IPC分类号： H03M13/00 , H03M13/13 , H03M13/11 , H03M13/05 , H03M13/21 , H03M13/15
CPC分类号： H03M13/13 , H03M13/05 , H03M13/1134 , H03M13/1137 , H03M13/1171 , H03M13/134 , H03M13/1515 , H03M13/21 , H03M13/6502 , H03M13/6561
摘要： An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.
摘要翻译：编码器模块包括顺序耦合的P / L奇偶校验移位寄存器，其中奇偶校验移位寄存器的第一奇偶移位寄存器的输入耦合到编码器模块的输入端，奇偶校验位的最后奇偶移位寄存器的输出移位寄存器耦合到编码器模块的输出，每个奇偶移位寄存器被配置为存储L个奇偶校验位。编码器模块还包括一个包括P / L奇偶校验生成模块的反馈电路，其中奇偶校验生成模块中的每一个通过开关耦合到奇偶移位寄存器中对应的一个的输出，并且还耦合到第一奇偶校验的输入移位寄存器，其中每个奇偶校验生成模块被配置为当其对应的开关闭合时，产生用于传输到第一奇偶移位寄存器的输入的L个奇偶校验位。

10. 发明授权

US08406334B1 Overflow resistant, fixed precision, bit optimized systolic array for QR decomposition and MIMO decoding 有权
标题翻译：用于QR分解和MIMO解码的溢流阻抗，固定精度，位优化收缩阵列
公开(公告)号：US08406334B1
公开(公告)日：2013-03-26
申请号：US12814319
申请日：2010-06-11
申请人： Raghavendar M. Rao , Raied N. Mazahreh , Hai-Jo Tarn
发明人： Raghavendar M. Rao , Raied N. Mazahreh , Hai-Jo Tarn
IPC分类号： H04B7/02 , H04L1/02
CPC分类号： H04B7/0854
摘要： In one embodiment, a circuit for matrix decomposition is provided. The circuit includes an input circuit for receiving a first matrix. A permutation circuit is coupled to the input circuit and configured to interchange columns of the first matrix according to a selected permutation to produce a second matrix. A systolic array is coupled to the permutation circuit and configured to perform QR decomposition of the second matrix to produce a third matrix and a fourth matrix. A reverse permutation circuit is coupled to the systolic array and configured to interchange rows of the third matrix according to an inverse of the selected permutation to produce a first factor matrix and interchange rows of the fourth matrix according to the inverse of the selected permutation to produce a second factor matrix.
摘要翻译：在一个实施例中，提供了一种用于矩阵分解的电路。该电路包括用于接收第一矩阵的输入电路。置换电路耦合到输入电路并且被配置为根据所选择的置换来交换第一矩阵的列，以产生第二矩阵。收缩阵列耦合到置换电路并且被配置为执行第二矩阵的QR分解以产生第三矩阵和第四矩阵。反向置换电路耦合到收缩阵列并且被配置为根据所选置换的倒数来交换第三矩阵的行以产生第一因子矩阵并且根据所选置换的倒数交换第四矩阵的行以产生第二个因素矩阵。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式