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1. 发明申请

WO2008033679A3 NON-VOLATILE MEMORY AND METHOD FOR REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE 审中-公开
公开(公告)号：WO2008033679A3
公开(公告)日：2008-03-20
申请号：PCT/US2007/077295
申请日：2007-08-30
申请人： SANDISK CORPORATION , LI, Yan , TU, Loc , HOOK, Charles Moana
发明人： LI, Yan , TU, Loc , HOOK, Charles Moana
IPC分类号： G11C16/10 , G11C29/50
摘要： High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

2. 发明申请

WO2008033693A2 NON-VOLATILE MEMORY AND METHOD FOR LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE 审中-公开
标题翻译：非易失性存储器和初始编程电压的线性估计方法
公开(公告)号：WO2008033693A2
公开(公告)日：2008-03-20
申请号：PCT/US2007/077449
申请日：2007-08-31
申请人： SANDISK CORPORATION , TU, Loc , HOOK, Charles, Moana , LI, Yan
发明人： TU, Loc , HOOK, Charles, Moana , LI, Yan
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C29/02 , G11C29/021 , G11C29/028
摘要： In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.
摘要翻译：在非易失性存储器中，字线上的所选页面通过阶梯波形的一系列电压脉冲被连续编程，在脉冲之间具有验证，直到页面被验证为指定图案。编程页面编程时的编程电压将用于估计页面起始编程电压的初始值。通过使用第二阶段第一阶段的估计来进一步细化该估计。而且，当测试在多个块上时，基于块的相似几何位置的字线采样可产生针对更快编程页面而优化的开始编程电压。

3. 发明申请

WO2013019713A1 MEMORY DIE SELF-DISABLE IF PROGRAMMABLE ELEMENT IS NOT TRUSTED 审中-公开
标题翻译：如果可编程元件未被触发，则存储器自动禁止
公开(公告)号：WO2013019713A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/048818
申请日：2012-07-30
申请人： SANDISK TECHNOLOGIES, INC. , TU, Loc , HOOK, Charles, Moana , THEIN, Nyi, Nyi
发明人： TU, Loc , HOOK, Charles, Moana , THEIN, Nyi, Nyi
IPC分类号： G11C29/00
CPC分类号： G11C29/832 , Y10T29/49004
摘要： Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.
摘要翻译：在本文中公开了在存储器管芯上用于指示存储器管芯是否有缺陷的可编程元件不能被信任的情况下，自动自身禁用存储器管芯的技术。存储器管芯具有芯片使能电路，以允许禁止特定存储器管芯。如果可编程元件可被信任，则可编程元件的状态被提供给芯片使能电路，以基于该状态启用/禁用存储器管芯。然而，如果可编程元件不能被信任，则芯片使能电路可以自动地禁用存储器管芯。这为多芯片存储器封装提供了更大的收益，因为仍然可以使用具有不可信任的可编程元件的存储器管芯的封装。

4. 发明申请

WO2008033693A3 NON-VOLATILE MEMORY AND METHOD FOR LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE 审中-公开
标题翻译：非易失性存储器和初始编程电压线性估计方法
公开(公告)号：WO2008033693A3
公开(公告)日：2008-08-07
申请号：PCT/US2007077449
申请日：2007-08-31
申请人： SANDISK CORP , TU LOC , HOOK CHARLES MOANA , LI YAN
发明人： TU LOC , HOOK CHARLES MOANA , LI YAN
IPC分类号： G11C16/12 , G11C16/04 , G11C16/34 , G11C29/02 , G11C29/50
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C29/02 , G11C29/021 , G11C29/028
摘要： In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.
摘要翻译：在非易失性存储器中，通过阶梯波形的一系列电压脉冲来连续地编程字线上的选定页面，同时在脉冲之间进行验证，直到页面被验证为指定图案。页面编程验证时的编程电压将是估计页面启动编程电压的初始值。通过在第二遍中使用来自第一遍的估计进一步改进估计。此外，当测试超过多个块时，基于块的类似几何位置的字线采样可以产生针对更快编程页面优化的起始编程电压。

5. 发明申请

WO2008033679A2 NON-VOLATILE MEMORY AND METHOD FOR REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE 审中-公开
标题翻译：非易失性存储器和方法在初始编程电压调整过程中减少擦除/写入循环
公开(公告)号：WO2008033679A2
公开(公告)日：2008-03-20
申请号：PCT/US2007077295
申请日：2007-08-30
申请人： SANDISK CORP , LI YAN , TU LOC , HOOK CHARLES MOANA
发明人： LI YAN , TU LOC , HOOK CHARLES MOANA
IPC分类号： G11C16/10 , G11C29/50
CPC分类号： G11C16/3454 , G11C16/04 , G11C16/0483 , G11C16/3481 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50004
摘要： High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.
摘要翻译：高性能非易失性存储器件具有为各种类型的存储器页和字线而修整的编程电压。每个可擦除存储器块中的一组字线在连续的程序循环中进行测试，以最大限度地减少产生过多擦除/编程周期的问题。对于给定类型的存储器页的最佳编程电压是从类似存储器页的样本的统计结果得出的。

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