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1. 发明授权

US08174090B2 Packaging structure 有权
标题翻译：包装结构
公开(公告)号：US08174090B2
公开(公告)日：2012-05-08
申请号：US12434199
申请日：2009-05-01
申请人： Zhiqi Wang , Guoqing Yu , Qiuhong Zou , Youjun Wang , Wei Wang
发明人： Zhiqi Wang , Guoqing Yu , Qiuhong Zou , Youjun Wang , Wei Wang
IPC分类号： H01L31/00
CPC分类号： H01L27/14687 , H01L24/13 , H01L27/14618 , H01L2224/05001 , H01L2224/05008 , H01L2224/0554 , H01L2224/05548 , H01L2224/05569 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2924/01028 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.
摘要翻译：本发明公开了一种包装结构和包装方法。封装结构包括焊料凸块，位于芯片前侧的焊盘和连接焊料凸块和焊盘的中间金属层，其中提供从芯片的背面通过焊盘的通孔并且中间金属层在通孔内连接到焊盘。在封装结构中，在芯片的背面形成通孔，露出芯片正面的焊盘，中间金属层与通孔内的焊盘连接。这提供了它们之间相对较大的接触面积。与现有技术的结构相比，这样形成的连接更可靠和稳定。

2. 发明申请

US20110006322A1 WAFER-LEVEL PACKAGE STRUCTURE OF LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：发光二极管的水平包装结构及其制造方法
公开(公告)号：US20110006322A1
公开(公告)日：2011-01-13
申请号：US12708943
申请日：2010-02-19
申请人： Junjie LI , Wenbin WANG , Qiuhong ZOU , Guoqing YU , Wei WANG
发明人： Junjie LI , Wenbin WANG , Qiuhong ZOU , Guoqing YU , Wei WANG
IPC分类号： H01L33/00 , H01L21/50
CPC分类号： H01L33/62 , H01L33/486 , H01L33/60 , H01L2224/16 , H01L2933/0033
摘要： A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires. The invention forms the leads on the second side of the substrate to extract the electrodes of the light emitting diode, that is, the light emitting diode and the leads thereof are located on the two opposite sides of the substrate in the technical solution of the invention, to thereby reduce the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.
摘要翻译：发光二极管的晶片级封装结构及其制造方法，封装结构包括：模具，其包括第一侧和与第一侧相对的第二侧; 在所述模具的第一侧上的第一绝缘层; 布置在绝缘层上并彼此电隔离的至少两根导线; 布置在导线上并适于与发光二极管的裸芯片的电极相对应地电连接的凸块; 在模具的第二面上的至少两个离散引线区域; 并且在引线区域中引线，彼此电隔离并且与导线相应地电连接。本发明在本发明的技术方案中在基板的第二面上形成引线以提取发光二极管的电极，即发光二极管及其引线位于基板的相对两侧，从而减小基板所需的面积; 并且可以在包装的后续结构中提取电极，而不需要金线，从而进一步减小包装的体积。

3. 发明申请

US20090289317A1 PACKAGING STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：包装结构及其制造方法
公开(公告)号：US20090289317A1
公开(公告)日：2009-11-26
申请号：US12233807
申请日：2008-09-19
申请人： Guoping YU , Zhiqi Wang , Guoqing Yu , Wei Wang , Qiuhong Zou
发明人： Guoping YU , Zhiqi Wang , Guoqing Yu , Wei Wang , Qiuhong Zou
IPC分类号： H01L31/02 , H01L21/50
CPC分类号： H01L27/14683 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L27/14618 , H01L2224/0401 , H01L2224/13022 , H01L2224/16 , H01L2924/14 , H01L2924/15311
摘要： The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.
摘要翻译：本发明提供了一种封装结构及其制造方法，封装结构包括芯片，设置在芯片上的兼容焊盘，与兼容焊盘电连接的中间金属层，焊料凸块和再分布金属层与焊料凸块电连接，其中再分布金属层直接与中间金属层连接以形成电连接。此外，再分布金属层和中间金属层之间的一些连接呈凹形，而再分布金属层与中间金属层之间的其它连接呈“ - ”形状，因此，连接增加，同时确保连接的稳定性。

4. 发明申请

US20080111223A1 Wafer Level Chip Size Packaged Chip Device With A Double-Layer Lead Structure And Method Of Fabricating The Same 有权
标题翻译：具有双层引线结构的晶片级芯片尺寸封装芯片器件及其制造方法
公开(公告)号：US20080111223A1
公开(公告)日：2008-05-15
申请号：US11559157
申请日：2006-11-13
申请人： Guoqing Yu , Youjun Wang , Qinqin Xu , Qingwei Wang , Wei Wang
发明人： Guoqing Yu , Youjun Wang , Qinqin Xu , Qingwei Wang , Wei Wang
IPC分类号： H01L23/02
CPC分类号： H01L23/525 , H01L23/3114 , H01L2924/0002 , H01L2924/00
摘要： The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.
摘要翻译：本发明公开了具有双层引线结构的晶片级芯片尺寸封装芯片器件及其制造方法。双层引线被设计为满足在半导体芯片上的周边阵列兼容焊盘面积增加的趋势，并且还可以在芯片底部表面上节省更多的用于布局引线的空间，以避免在增加中发生的潜在的短路在单层铅条件下每面积数量增加的概率。

5. 发明申请

US20090102056A1 Patterned Leads For WLCSP And Method For Fabricating The Same 审中-公开
标题翻译：用于WLCSP的图案引线及其制造方法
公开(公告)号：US20090102056A1
公开(公告)日：2009-04-23
申请号：US12135331
申请日：2008-06-09
申请人： Guoping Yu , Guoqing Yu , Qinqin Xu , Wenlong Wang , Wei Wang
发明人： Guoping Yu , Guoqing Yu , Qinqin Xu , Wenlong Wang , Wei Wang
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L27/14618 , H01L24/05 , H01L24/13 , H01L27/14683 , H01L29/0657 , H01L2224/0401 , H01L2924/01327 , H01L2924/10253 , H01L2924/14
摘要： The present invention provides patterned leads for a wafer level chip size package and methods for fabricating the same. The patterned leads include connection leads and solder pads. In designing, a compensation pattern is disposed on the connection lead or on the solder pad, so as to increase the distance between the connection lead and the solder pad. The present invention meets a tendency of increasing quantity per area of peripheral arrayed compatible pads and solder bumps on a semiconductor chip, and also saves more space for layout of leads on the chip bottom surface so as to avoid potential short circuit in between which happens in increasing probability with increasing quantity per area on the condition of the lead and the solder bump.
摘要翻译：本发明提供了晶片级芯片尺寸封装的图案引线及其制造方法。图案化的引线包括连接引线和焊盘。在设计中，在连接引线或焊盘上设置补偿图案，以便增加连接引线和焊盘之间的距离。本发明满足了在半导体芯片上周边排列的兼容焊盘和焊料凸块的面积增加的趋势，并且还节省了用于在芯片底表面上布置引线的更多空间，以避免在两者之间发生潜在的短路在引线和焊料凸块的条件下，每个面积的数量增加的概率增加。

6. 发明申请

US20090080846A1 Optical Waveguide and Method for Manufacturing the Same 审中-公开
标题翻译：光波导及其制造方法
公开(公告)号：US20090080846A1
公开(公告)日：2009-03-26
申请号：US12019693
申请日：2008-01-25
申请人： Mingda Shao , Guoqing Yu , Qinqin Xu , Wenlong Wang , Wei Wang
发明人： Mingda Shao , Guoqing Yu , Qinqin Xu , Wenlong Wang , Wei Wang
IPC分类号： G02B6/036 , G02B6/02
CPC分类号： G02B6/136 , G02B6/1221 , G02B6/4214 , G02B6/43
摘要： The present invention provides a wafer level optical waveguide and a method for manufacturing the same, wherein it can be realized by employing manufacture process for semiconductor integrated circuits to manufacture a micron optical waveguide with a smooth interface, uniform thickness and a mirror-like end with any angle, and to remarkably reduce its manufacture cost at the meantime.
摘要翻译：本发明提供一种晶片级光波导及其制造方法，其可以通过采用半导体集成电路的制造工艺来制造具有平滑界面，均匀厚度和镜面端的微米光波导，任何角度，并同时显着降低其制造成本。

7. 发明申请

US20080111228A1 Wafer Level Chip Size Packaged Chip Device With An N-Shape Junction Inside And Method Of Fabricating The Same 有权
标题翻译：晶圆级芯片尺寸封装芯片器件与N型结内部及其制造方法
公开(公告)号：US20080111228A1
公开(公告)日：2008-05-15
申请号：US11559129
申请日：2006-11-13
申请人： Guoqing Yu , Youjun Wang , Qinqin Xu , Qingwei Wang , Wei Wang
发明人： Guoqing Yu , Youjun Wang , Qinqin Xu , Qingwei Wang , Wei Wang
IPC分类号： H01L23/043 , H01L21/58
CPC分类号： H01L23/3114 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/13022 , H01L2924/01078 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.
摘要翻译：本发明提供了具有N形结的晶片级芯片尺寸封装芯片器件，外部引线电连接到外围阵列兼容焊盘及其制造方法。在晶片级芯片尺寸封装中，采用这种n形结代替了壳式晶圆级芯片尺寸封装技术中观察到的传统T形结，由于连接面积较大，兼容焊盘与外部引线之间的电气连接更加可靠比T形连接处的对应物。

8. 发明申请

US20160128933A1 Therapeutic Methods and Compositions 审中-公开
标题翻译：治疗方法和组成
公开(公告)号：US20160128933A1
公开(公告)日：2016-05-12
申请号：US14536709
申请日：2014-11-10
申请人： Tiangang Shang , Guoqing Yu
发明人： Tiangang Shang , Guoqing Yu
IPC分类号： A61K9/00 , A61K9/70 , A61K31/125 , A61K31/045 , A61K31/35 , A61K31/122 , A61K31/11 , A61K31/194 , A61K31/365 , A61K31/69 , A61K31/05 , A61K31/015 , A61K31/085 , A61K31/12
CPC分类号： A61K9/0014 , A61K9/08 , A61K9/7061 , A61K31/01 , A61K31/015 , A61K31/045 , A61K31/05 , A61K31/085 , A61K31/11 , A61K31/12 , A61K31/122 , A61K31/125 , A61K31/194 , A61K31/35 , A61K31/352 , A61K31/365 , A61K31/366 , A61K31/69 , A61K47/10 , A61K2300/00
摘要： Methods and compositions are described for stimulating therapeutic points of a mammal subject by applying therapeutically effective amount of one or more TRP channel agonists.
摘要翻译：描述了通过应用治疗有效量的一种或多种TRP通道激动剂来刺激哺乳动物受试者的治疗点的方法和组合物。

9. 发明申请

US20100133640A1 PACKAGING METHOD AND PACKAGING STRUCTURE 有权
标题翻译：包装方法和包装结构
公开(公告)号：US20100133640A1
公开(公告)日：2010-06-03
申请号：US12434199
申请日：2009-05-01
申请人： Zhiqi Wang , Guoqing Yu , Qiuhong Zou , Youjun Wang , Wei Wang
发明人： Zhiqi Wang , Guoqing Yu , Qiuhong Zou , Youjun Wang , Wei Wang
IPC分类号： H01L31/0224 , H01L21/768
CPC分类号： H01L27/14687 , H01L24/13 , H01L27/14618 , H01L2224/05001 , H01L2224/05008 , H01L2224/0554 , H01L2224/05548 , H01L2224/05569 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2924/01028 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.
摘要翻译：本发明公开了一种包装结构和包装方法。封装结构包括焊料凸块，位于芯片前侧的焊盘和连接焊料凸块和焊盘的中间金属层，其中提供从芯片的背面通过焊盘的通孔并且中间金属层在通孔内连接到焊盘。在封装结构中，在芯片的背面形成通孔，露出芯片正面的焊盘，中间金属层与通孔内的焊盘连接。这提供了它们之间相对较大的接触面积。与现有技术的结构相比，这样形成的连接更可靠和稳定。

10. 发明申请

US20100065956A1 PACKAGING STRUCTURE, PACKAGING METHOD AND PHOTOSENSITIVE DEVICE 审中-公开
标题翻译：包装结构，包装方法和感光装置
公开(公告)号：US20100065956A1
公开(公告)日：2010-03-18
申请号：US12412778
申请日：2009-03-27
申请人： Zhiqi WANG , Guoqing Yu , Qiuhong Zou , Wei Wang
发明人： Zhiqi WANG , Guoqing Yu , Qiuhong Zou , Wei Wang
IPC分类号： H01L23/485 , H01L21/50
CPC分类号： H01L27/14618 , H01L24/16 , H01L27/14627 , H01L27/14636 , H01L27/14683 , H01L27/14685 , H01L31/0203 , H01L31/0232 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/3025 , H01L2224/05099 , H01L2924/01028
摘要： The application provides a packaging structure, a packaging method and a photosensitive device. The packaging structure includes a substrate structure, a chip and a solder bump electrically connecting with a pad on the chip. The solder bump is located on the substrate structure, so that the multilayer coverage structure required when forming a bump on a side of the chip in the prior art packaging structure is avoided. In this way, the thickness of the packaging structure is reduced and the reliably of the packaging structure is improved.
摘要翻译：该应用提供包装结构，包装方法和感光装置。封装结构包括与芯片上的焊盘电连接的衬底结构，芯片和焊料凸块。焊料凸块位于衬底结构上，从而避免了在现有技术的封装结构中在芯片侧面形成凸块所需的多层覆盖结构。以这种方式，减小了包装结构的厚度，提高了包装结构的可靠性。

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