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1. 发明授权

US06352910B1 Method of depositing amorphous silicon based films having controlled conductivity 失效
标题翻译：沉积具有受控导电性的非晶硅基膜的方法
公开(公告)号：US06352910B1
公开(公告)日：2002-03-05
申请号：US09249041
申请日：1999-02-12
申请人： William R. Harshbarger , Takako Takehara , Jeff C. Olsen , Regina Qiu , Yvonne LeGrice , Guofu J. Feng , Robert M. Robertson , Kam Law
发明人： William R. Harshbarger , Takako Takehara , Jeff C. Olsen , Regina Qiu , Yvonne LeGrice , Guofu J. Feng , Robert M. Robertson , Kam Law
IPC分类号： H01L2120
CPC分类号： C23C16/24
摘要： Deposition methods for preparing amorphous silicon based films with controlled resistivity and low stress are described. Such films can be used as the interlayer in FED manufacturing. They can also be used in other electronic devices which require films with controlled resistivity in the range between those of an insulator and of a conductor. The deposition methods described in the present invention employ the method of chemical vapor deposition or plasma-enhanced chemical vapor deposition; other film deposition techniques, such as physical vapor deposition, also may be used. In one embodiment, an amorphous silicon-based film is formed by introducing into a deposition chamber a silicon-based volatile, a conductivity-increasing volatile including one or more components for increasing the conductivity of the amorphous silicon-based film, and a conductivity-decreasing volatile including one or more components for decreasing the conductivity of the amorphous silicon-based film.
摘要翻译：描述了制备具有受控电阻率和低应力的非晶硅基膜的沉积方法。这种膜可用作FED制造中的中间层。它们也可用于需要具有在绝缘体和导体之间的范围内的受控电阻率的膜的其它电子器件。本发明中描述的沉积方法采用化学气相沉积或等离子体增强化学气相沉积的方法; 也可以使用其它成膜技术，例如物理气相沉积。在一个实施方案中，通过向沉积室中引入硅基挥发物，包含一种或多种用于增加非晶硅基膜的导电性的组分的增加电导率的挥发性，并且导电性 - 降低挥发性，包括一种或多种用于降低非晶硅基膜的导电性的组分。

2. 发明授权

US5567476A Multi-step chemical vapor deposition method for thin film transistors 失效
标题翻译：薄膜晶体管的多步骤化学气相沉积方法
公开(公告)号：US5567476A
公开(公告)日：1996-10-22
申请号：US427772
申请日：1995-04-25
申请人： Kam S. Law , Robert Robertson , Michael Kollrack , Angela T. Lee , Takako Takehara , Guofu J. Feng , Dan Maydan
发明人： Kam S. Law , Robert Robertson , Michael Kollrack , Angela T. Lee , Takako Takehara , Guofu J. Feng , Dan Maydan
IPC分类号： H01L21/205 , C23C16/24 , C23C16/34 , H01L21/31 , H01L21/318 , H01L21/336 , H01L29/786 , C23C16/00
CPC分类号： H01L29/66765 , C23C16/24 , C23C16/345
摘要： A multi-step CVD method for thin film transistor is disclosed. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.
摘要翻译：公开了薄膜晶体管的多步CVD方法。该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。

3. 发明授权

US5589233A Single chamber CVD process for thin film transistors 失效
标题翻译：用于薄膜晶体管的单室CVD工艺
公开(公告)号：US5589233A
公开(公告)日：1996-12-31
申请号：US466915
申请日：1995-06-06
申请人： Kam Law , Robert Robertson , Guofu J. Feng
发明人： Kam Law , Robert Robertson , Guofu J. Feng
IPC分类号： C23C16/44 , H01L21/205 , H01L21/336 , H01L29/786 , C23C16/00 , B05D3/06
CPC分类号： H01L29/66765 , C23C16/4404 , H01L21/02422 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , Y10S438/905
摘要： A method of depositing layers of intrinsic amorphous silicon and doped amorphous silicon sequentially on a substrate in the same CVD chamber without incurring a dopant contamination problem. The method can be carried out by first depositing an additional layer of a dielectric insulating material prior to the deposition process of the intrinsic amorphous silicon layer. The additional layer of insulating material deposited on the substrate should have a thickness such that residual insulating material coated on the chamber walls is sufficient to cover the residual dopants on the chamber walls left by the deposition process of the previous substrate. This provides a clean environment for the next deposition process of an intrinsic amorphous silicon layer on a substrate in the same CVD chamber.
摘要翻译：本征非晶硅和掺杂的非晶硅的顺序沉积在相同CVD室中的衬底上的方法，而不会引起掺杂剂污染问题。该方法可以通过在本征非晶硅层的沉积工艺之前首先沉积介电绝缘材料的附加层来进行。沉积在基板上的附加绝缘材料层应该具有使得涂覆在室壁上的残留绝缘材料足以覆盖由先前基板的沉积工艺留下的室壁上的残留掺杂剂的厚度。这为在同一CVD室中的衬底上的本征非晶硅层的下一个沉积工艺提供了清洁的环境。

4. 发明授权

US5441768A Multi-step chemical vapor deposition method for thin film transistors 失效
标题翻译：薄膜晶体管的多步骤化学气相沉积方法
公开(公告)号：US5441768A
公开(公告)日：1995-08-15
申请号：US193310
申请日：1994-02-08
申请人： Kam S. Law , Robert Robertson , Michael Kollrack , Angela T. Lee , Takako Takehara , Guofu J. Feng , Dan Maydan
发明人： Kam S. Law , Robert Robertson , Michael Kollrack , Angela T. Lee , Takako Takehara , Guofu J. Feng , Dan Maydan
IPC分类号： H01L21/205 , C23C16/24 , C23C16/34 , H01L21/31 , H01L21/318 , H01L21/336 , H01L29/786 , C23C16/22
CPC分类号： H01L29/66765 , C23C16/24 , C23C16/345
摘要： An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.
摘要翻译：提供了一种在保持优异的膜质量的同时以高沉积速率在薄膜晶体管基板上沉积栅极氮化硅和非晶硅的膜的改进方法。在非晶硅和氮化物之间的界面附近的材料以低沉积速率沉积，其产生优质的膜。离开界面的区域以高沉积速率沉积，其产生较小但仍然是优质的膜。通过使用该方法，能够以非常高的效率制造出优质的薄膜晶体管。该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。

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