会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR
    • 增强型绝缘栅结构场效应晶体管
    • US20080203430A1
    • 2008-08-28
    • US11781338
    • 2007-07-23
    • Grigory SiminMichael ShurRemigijus Gaska
    • Grigory SiminMichael ShurRemigijus Gaska
    • H01L29/778
    • H01L29/7783H01L29/2003H01L29/402
    • Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.
    • 本发明的方面提供了一种在零栅极偏压,低栅极电流和/或高可靠性下具有低功耗的增强模式(E模式)绝缘栅(IG)双异质结构场效应晶体管(DHFET)。 根据本发明的实施例的E型HFET包括:顶部和底部阻挡层; 以及夹在底部和顶部阻挡层之间的沟道层,其中底部和顶部势垒层具有比沟道层更大的带隙,并且其中底部势垒层的极化电荷消耗沟道层和顶部势垒的极化电荷 层在沟道层中诱导载流子; 并且其中底部阻挡层中的总极化电荷大于顶部势垒层中的总极化电荷,使得沟道层在零栅极偏压下基本上耗尽。