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1. 发明授权

US08140767B2 Cache management through delayed writeback 有权
标题翻译：缓存管理通过延迟回写
公开(公告)号：US08140767B2
公开(公告)日：2012-03-20
申请号：US12478555
申请日：2009-06-04
申请人： Gordon Bernard Bell , Anil Krishna , Brian Michael Rogers , Ken Van Vu
发明人： Gordon Bernard Bell , Anil Krishna , Brian Michael Rogers , Ken Van Vu
IPC分类号： G06F12/08
CPC分类号： G06F12/121
摘要： The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a threshold activity level. A least important cache line is located in the cache responsive to a determination that the threshold activity level is exceeded, wherein the least important cache line is located using a cache replacement scheme. It is determined whether the least important cache line is clean responsive to the determination that the threshold activity level is exceeded. The least important cache line is selected for replacement in the cache responsive to a determination that the least important cache line is clean. A clean cache line is located within a subset of the number of cache lines and selecting the clean cache line for replacement responsive to an absence of a determination that the least important cache line is not clean, wherein the each cache line in the subset is examined in ascending order of importance according to the cache replacement scheme.
摘要翻译：说明性实施例提供了用于管理高速缓存中的多条高速缓存行的方法，装置和计算机程序产品。在一个说明性实施例中，确定与高速缓存通信的存储器总线上的活动是否超过阈值活动级别。响应于确定超过了阈值活动级别，至少重要的高速缓存行位于缓存中，其中使用高速缓存替换方案来定位最不重要的高速缓存行。响应于超过阈值活动水平的确定，确定最不重要的高速缓存行是否是干净的。响应于确定最不重要的高速缓存行是干净的，在缓存中选择最不重要的高速缓存行用于替换。干净的高速缓存行位于高速缓存行数量的一个子集内，并且响应于不存在最不重要的高速缓存行不干净的确定而选择用于替换的干净高速缓存行，其中检查子集中的每个高速缓存行按照缓存替换方案的重要性升序排列。

2. 发明授权

US08200905B2 Effective prefetching with multiple processors and threads 失效
标题翻译：有效的预取与多个处理器和线程
公开(公告)号：US08200905B2
公开(公告)日：2012-06-12
申请号：US12192072
申请日：2008-08-14
申请人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译：处理系统包括被配置为处理应用的存储器和第一核心。第一个核心包括第一个缓存。处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

3. 发明申请

US20120246406A1 EFFECTIVE PREFETCHING WITH MULTIPLE PROCESSORS AND THREADS 失效
标题翻译：有效的预处理与多个处理器和螺纹
公开(公告)号：US20120246406A1
公开(公告)日：2012-09-27
申请号：US13488215
申请日：2012-06-04
申请人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon Bernard Bell , Gordon Taylor Davis , Jeffrey Haskell Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译：处理系统包括被配置为处理应用的存储器和第一核心。第一个核心包括第一个缓存。处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

4. 发明申请

US20100042786A1 SNOOP-BASED PREFETCHING 失效
标题翻译：基于SNOOP的预选
公开(公告)号：US20100042786A1
公开(公告)日：2010-02-18
申请号：US12192072
申请日：2008-08-14
申请人： Gordon Bernard BELL , Gordon Taylor DAVIS , Jeffrey Haskell DERBY , Anil KRISHNA , Srinivasan RAMANI , Ken VU , Steve WOOLET
发明人： Gordon Bernard BELL , Gordon Taylor DAVIS , Jeffrey Haskell DERBY , Anil KRISHNA , Srinivasan RAMANI , Ken VU , Steve WOOLET
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system is disclosed. The processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译：公开了一种处理系统。处理系统包括被配置为处理应用的存储器和第一核心。第一个核心包括第一个缓存。处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

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