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    • 9. 发明授权
    • Parallel memory device for image processing utilizing linear
transformation
    • 使用线性变换的图像处理的并行存储器件
    • US5933861A
    • 1999-08-03
    • US949542
    • 1997-10-14
    • Heung Gyu LeeJong Won ParkGil Yoon Kim
    • Heung Gyu LeeJong Won ParkGil Yoon Kim
    • G06F12/00G06F15/76G06F17/16G06T1/60G11C15/00G06F15/16
    • G06T1/60
    • A parallel memory device for an image processing utilizing a linear transformation, capable of achieving simultaneous access in either of various access forms which uses simple hardware and is capable of achieving a high processing rate and thereby a high circuit efficiency. The parallel memory device includes a plurality of address computation circuit units, each adapted to generate an address of each corresponding one of memory modules on the basis of an access form, reference coordinates and a memory module number of the corresponding memory module, a plurality of memory cells each adapted to receive the address generated from each corresponding one of the address computation circuit units and a read/write signal and execute storage, inputting and outputting of actual data, omega networks each adapted to receive the data from the memory cells associated therewith, to generate appropriate paths for the data such that an actual processing order of the memory modules coincides with a logical order required for a processor, and to output the data via the generated paths, and a shift circuit unit adapted to generate appropriate paths between each omega network and data terminals on the basis of an input indicative of the access form.
    • 一种用于利用线性变换的图像处理的并行存储器件,能够实现使用简单硬件的各种存取形式中的任何一种的同时访问,并能够实现高处理速率,从而实现高电路效率。 并行存储器件包括多个地址计算电路单元,每个地址计算电路单元适于基于访问形式,对应存储器模块的参考坐标和存储器模块号码生成每个对应的一个存储器模块的地址,多个 每个存储单元适于接收从地址计算电路单元中的每个对应的一个地址产生的地址和读/写信号,并执行实际数据的存储,输入和输出,每个适于从与其相关联的存储器单元接收数据的ω网络 以产生数据的适当路径,使得存储器模块的实际处理顺序与处理器所需的逻辑顺序一致,并经由所生成的路径输出数据;以及移位电路单元,适于在每个 基于表示访问表单的输入的欧米茄网络和数据终端。