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1. 发明授权

US07158535B1 System and method for translating overhead bytes in a multidimensional digital frame structure 有权
标题翻译：用于在多维数字帧结构中翻译开销字节的系统和方法
公开(公告)号：US07158535B1
公开(公告)日：2007-01-02
申请号：US09746159
申请日：2000-12-22
申请人： George Beshara Bendak , Alan Michael Sorgi
发明人： George Beshara Bendak , Alan Michael Sorgi
IPC分类号： H04J3/06 , H04L12/56
CPC分类号： H04J3/1617 , H04L69/08 , H04L69/12 , H04L69/18
摘要： A system and method have been provided for translating digitally wrapped communications between networks using different protocols. This invention makes use of an integrated circuit (IC) relay with programmable features to modify the locations and functions of overhead bytes between the receive and transmit sides of the device, permitting two dissimilar networks to be bridged. That is, the IC relay converts frame formatting from one frame structure to another, so that incompatible networks can communicate.
摘要翻译：已经提供了一种用于在使用不同协议的网络之间翻译数字封装通信的系统和方法。本发明利用具有可编程特征的集成电路（IC）继电器来修改设备的接收侧和发送侧之间的开销字节的位置和功能，从而允许桥接两个不同的网络。也就是说，IC中继将帧格式从一帧结构转换到另一帧结构，使得不兼容的网络可以通信。

2. 发明授权

US06993700B1 System and method for generating forward error correction based alarms 失效
标题翻译：用于产生基于前向纠错的报警的系统和方法
公开(公告)号：US06993700B1
公开(公告)日：2006-01-31
申请号：US10037959
申请日：2001-12-21
申请人： Andrew Mark Player , George Beshara Bendak
发明人： Andrew Mark Player , George Beshara Bendak
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H04L1/0045
摘要： A system and method are provided for generating alarms from forward error correction (FEC) data in a G.709 network-connected integrated circuit. The method includes: receiving messages including forward error correction bytes; using the forward error correction bytes to detect errors in the messages; and, generating alarm signals in response to the detected errors. Generating alarm signals in response to the detected errors includes generating a signal degrade (SD) signal in response to detecting a first number of errors (error density) within a predetermined time period. Likewise, generating alarm signals in response to the detected errors includes generating a signal fail (SF) signal in response to detecting a second number of errors (second error density), greater than the first number, within the predetermined time period. The method further includes: selecting an error type. Then, alarm signals are generated in response to the selected error type. The error types include a “1s” density alarm, a “0s” density alarm, a bytes density alarm, and a sub-row density alarm.
摘要翻译：提供了一种用于从G.709网络连接集成电路中的前向纠错（FEC）数据产生报警的系统和方法。该方法包括：接收包括前向纠错字节的消息; 使用前向纠错字节来检测消息中的错误; 并响应于检测到的错误产生报警信号。响应于检测到的错误产生报警信号包括响应于在预定时间段内检测到第一数量的错误（误差密度）产生信号降级（SD）信号。类似地，响应于检测到的错误产生报警信号包括响应于在预定时间段内检测大于第一数量的第二数量的误差（第二误差密度）来产生信号故障（SF）信号。该方法还包括：选择错误类型。然后，响应所选择的错误类型产生报警信号。错误类型包括“1s”密度报警，“0s”浓度报警，字节密度报警和子行密度报警。

3. 发明授权

US07058090B1 System and method for paralleling digital wrapper data streams 有权
标题翻译：用于并行数字包装数据流的系统和方法
公开(公告)号：US07058090B1
公开(公告)日：2006-06-06
申请号：US10023675
申请日：2001-12-18
申请人： Andrew Mark Player , Alan Michael Sorgi , George Beshara Bendak
发明人： Andrew Mark Player , Alan Michael Sorgi , George Beshara Bendak
IPC分类号： H04J3/04
CPC分类号： H04J3/062 , H04J3/1611
摘要： A system and method are provided for paralleling data streams in a G.709 network of connected integrated circuits. The system comprises a demultiplexer for receiving a first digital wrapper data stream having a first data rate. The demultiplexer demultiplexes the first data stream into a second plurality of digital wrapper data streams having a second data rate, less than the first data rate. A second plurality of processors each accept a corresponding one of the second plurality of data streams and supply a processed data stream at the second data rate. The demultiplexer receives frame alignment signal bytes in the overhead of every first data stream frame and synchronizes frame alignment signal bytes in each of the second plurality of data streams to the frame alignment signal bytes in the first data stream.
摘要翻译：提供了一种用于在连接的集成电路的G.709网络中并行数据流的系统和方法。该系统包括用于接收具有第一数据速率的第一数字包装数据流的解复用器。解复用器将第一数据流解复用为具有小于第一数据速率的第二数据速率的第二多个数字封装数据流。第二多个处理器各自接受第二多个数据流中的对应的一个，并以第二数据速率提供经处理的数据流。解复用器在每个第一数据流帧的开销中接收帧对准信号字节，并将第二多个数据流中的每一个中的帧对准信号字节同步到第一数据流中的帧对准信号字节。

4. 发明授权

US06961366B1 System and method for redundant path connections in digital communications network 有权
标题翻译：数字通信网络中冗余路径连接的系统和方法
公开(公告)号：US06961366B1
公开(公告)日：2005-11-01
申请号：US09753185
申请日：2001-01-02
申请人： George Beshara Bendak , Alan Michael Sorgi
发明人： George Beshara Bendak , Alan Michael Sorgi
IPC分类号： H04L25/60
CPC分类号： H04L25/20 , H04L25/0272
摘要： A system and method for providing redundancy in an integrated circuit (IC) relay device has been disclosed. The relay device accepts communications on a first and second receive path. The relay device monitors communications on both the receive paths, and selects a path having a high degree of integrity. Likewise, the relay selectively supplies communications on a first and second transmit path. The relay device selects the transmit path having the proper measure of communication integrity. Communications integrity can be based upon internally monitored criteria such as bit error rate, synchronization, clock signals, and forward error correction. Alternately, the integrity is determined external to the relay, and the relay responds to external switch commands.
摘要翻译：已经公开了用于在集成电路（IC）中继装置中提供冗余的系统和方法。中继设备接受第一和第二接收路径上的通信。中继设备监视两个接收路径上的通信，并选择具有高度完整性的路径。类似地，继电器选择性地在第一和第二发射路径上提供通信。中继设备选择具有适当测量通信完整性的发送路径。通信完整性可以基于内部监控的标准，例如误码率，同步，时钟信号和前向纠错。或者，完整性在继电器外部确定，继电器响应外部开关指令。

5. 发明授权

US06847657B1 System and method for programming synchronization criteria in a multidimensional digital frame structure 有权
标题翻译：用于在多维数字帧结构中编程同步标准的系统和方法
公开(公告)号：US06847657B1
公开(公告)日：2005-01-25
申请号：US09745774
申请日：2000-12-22
申请人： George Beshara Bendak , Alan Michael Sorgi
发明人： George Beshara Bendak , Alan Michael Sorgi
IPC分类号： H04J3/06
CPC分类号： H04J3/0608
摘要： A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the number of frames, with recognizable frame synchronization bytes (FSBs), required for synchronization to be made programmable, so that the system and method are flexible for changes in communication protocols. This flexibility also impacts the number, value, location, bandwidth, and the bit error rate (BER) of the located FSBs.
摘要翻译：已经提供了一种用于编程多维数字帧结构的同步特征的系统和方法。这样的帧结构充当数字封装，并且包括开销，有效载荷和前向纠错（FEC）部分。开销部分中的字用于同步帧结构。所描述的发明允许使可同步的可识别帧同步字节（FSB）的帧数可编程，使得系统和方法对于通信协议的改变是灵活的。这种灵活性还会影响所在FSB的数量，价值，位置，带宽和误码率（BER）。

6. 发明授权

US07352694B1 System and method for tolerating data link faults in a packet communications switch fabric 有权
标题翻译：用于容忍数据包通信交换结构中的数据链路故障的系统和方法
公开(公告)号：US07352694B1
公开(公告)日：2008-04-01
申请号：US10373139
申请日：2003-02-24
申请人： Philip Michael Clovis , Eli James Aubrey Fernald , John David Huber , Kirk Alvin Miller , Sushil Kumar Singh , Prayag Bhanubhai Patel , Kenneth Yi Yun , George Beshara Bendak
发明人： Philip Michael Clovis , Eli James Aubrey Fernald , John David Huber , Kirk Alvin Miller , Sushil Kumar Singh , Prayag Bhanubhai Patel , Kenneth Yi Yun , George Beshara Bendak
IPC分类号： G01R31/08 , G06F11/00
CPC分类号： H04L49/252 , G06F8/34 , H04L49/205 , H04L49/3018 , H04L49/3027 , H04L49/503
摘要： A system and method are provided for tolerating data line faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of ingress port card ports, the plurality of information packets addressing a plurality of egress port card ports; selectively connecting port card ports to port card backplane data links; selectively connecting port card backplane data links and crossbars; sensing a connection fault in a backplane data link; in response to sensing the fault, reselecting connections between the port card ports and the port card backplane data links; in response to reselecting connections between the port card ports and the port card backplane data links, serially transferring packets through the port cards; serially transferring packets through the crossbars to the egress port cards; and, suspending use of the faulty connection.
摘要翻译：提供了一种用于容忍分组通信交换结构中的数据线路故障的系统和方法。所述方法包括：在多个入口端口卡端口处接收包括多个小区的信息分组，所述多个信息分组寻址多个出口端口卡端口; 选择性地将端口卡端口连接到端口卡背板数据链路; 有选择地连接端口卡背板数据链接和交叉栏; 感测背板数据链路中的连接故障; 响应感测故障，重新选择端口卡端口和端口卡背板数据链路之间的连接; 响应重新选择端口卡端口和端口卡背板数据链路之间的连接，通过端口卡串行传输数据包; 将数据包通过十字准线串行传输到出口端口卡; 并暂停使用故障连接。

7. 发明授权

US07230947B1 Minimum latency cut-through switch fabric 有权
标题翻译：最小延迟直通交换矩阵
公开(公告)号：US07230947B1
公开(公告)日：2007-06-12
申请号：US10378502
申请日：2003-03-03
申请人： John David Huber , Kirk Alvin Miller , Michael John Hellmer , Kenneth Yi Yun , Kevin Warren James , George Beshara Bendak
发明人： John David Huber , Kirk Alvin Miller , Michael John Hellmer , Kenneth Yi Yun , Kevin Warren James , George Beshara Bendak
IPC分类号： H04Q11/00
CPC分类号： H04L12/5601 , H04L49/106 , H04L2012/5665 , H04L2012/5675
摘要： A system and method are provided for cut-through packet routing in a packet communications switch fabric. The method comprises: accepting information packets addressed to a plurality of output port card egress ports at an input port card ingress port; routing information packets between port cards on backplane data links through an intervening crossbar; maintaining a credit counter for each port card egress destination, at the input port card; decrementing the counter in response to transmitting cells in a packet from the input port card; and, incrementing the counter in response to transmitting cells from the packet at the output port card. In some aspects of the method, accepting information includes buffering the packets in an ingress memory subsystem (iMS). Routing information includes the iMS transmitting buffered packets on a selected backplane data link. Decrementing the counter includes the iMS communicating with the iPQ in response to transmitting a cell.
摘要翻译：提供了一种用于分组通信交换结构中的直通分组路由的系统和方法。该方法包括：接收寻址到输入端口卡入口的多个输出端口卡出口端口的信息包; 在背板数据链路上的端口卡之间通过插入的交叉开关路由信息包; 在输入端口卡上维护每个端口卡出口目的地的信用计数器; 响应于来自输入端口卡的分组中的传输小区而递减计数器; 并且响应于从输出端口卡处的分组发送小区而递增计数器。在该方法的某些方面，接收信息包括缓冲入口存储器子系统（iMS）中的分组。路由信息包括在选定的背板数据链路上发送缓冲的分组的iMS。减少计数器包括响应于传输单元而与iPQ通信的iMS。

8. 发明授权

US07054336B1 System and method for programming the quantity of frame synchronization words in a multidimensional digital frame structure 有权
标题翻译：用于在多维数字帧结构中编程帧同步字数量的系统和方法
公开(公告)号：US07054336B1
公开(公告)日：2006-05-30
申请号：US09746152
申请日：2000-12-22
申请人： George Beshara Bendak , Alan Michael Sorgi
发明人： George Beshara Bendak , Alan Michael Sorgi
IPC分类号： H04J3/06
CPC分类号： H04L1/0083 , H04J3/0605
摘要： A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the quantity of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols.
摘要翻译：已经提供了一种用于编程多维数字帧结构的同步特征的系统和方法。这样的帧结构充当数字封装，并且包括开销，有效载荷和前向纠错（FEC）部分。开销部分中的字用于同步帧结构。所描述的发明允许帧同步字节（FSB）的量可编程，使得系统和方法对于通信协议的改变是灵活的。

9. 发明授权

US06973099B1 System and method for programming the value of frame synchronization words in a multidimensional digital frame structure 有权
标题翻译：用于在多维数字帧结构中对帧同步字的值进行编程的系统和方法
公开(公告)号：US06973099B1
公开(公告)日：2005-12-06
申请号：US09745655
申请日：2000-12-22
申请人： George Beshara Bendak , Alan Michael Sorgi
发明人： George Beshara Bendak , Alan Michael Sorgi
IPC分类号： H04J3/06 , H04L7/04
CPC分类号： H04L7/042 , H04J3/0605
摘要： A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the value of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols. This flexibility also impacts the quantity, the location, bandwidth, and the bit error rate (BER) of the FSBs.
摘要翻译：已经提供了一种用于编程多维数字帧结构的同步特征的系统和方法。这种帧结构充当数字封装，并且包括开销，有效载荷和前向纠错（FEC）部分。开销部分中的字用于同步帧结构。所描述的发明允许帧同步字节（FSB）的值可编程，使得系统和方法对于通信协议的改变是灵活的。这种灵活性还会影响FSB的数量，位置，带宽和误码率（BER）。

10. 发明授权

US06965618B1 System and method for programming the bit error rate of frame synchronization words in a multidimensional digital frame structure 有权
标题翻译：用于在多维数字帧结构中编程帧同步字的误码率的系统和方法
公开(公告)号：US06965618B1
公开(公告)日：2005-11-15
申请号：US09747380
申请日：2000-12-22
申请人： George Beshara Bendak , Alan Michael Sorgi
发明人： George Beshara Bendak , Alan Michael Sorgi
IPC分类号： H04J3/06 , H04L1/20 , H04L12/56
CPC分类号： H04J3/0605 , H04L1/203
摘要： A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the bit error rate (BER) of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols. This flexibility also impacts the number, the location, bandwidth, and the value the FSBs.
摘要翻译：已经提供了一种用于编程多维数字帧结构的同步特征的系统和方法。这种帧结构充当数字封装，并且包括开销，有效载荷和前向纠错（FEC）部分。开销部分中的字用于同步帧结构。所描述的发明允许帧同步字节（FSB）的误码率（BER）可编程，使得系统和方法对于通信协议的改变是灵活的。这种灵活性也会影响FSB的数量，位置，带宽和价值。

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