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    • 4. 发明授权
    • Timing device and timing method
    • 定时装置和定时方法
    • US06621806B1
    • 2003-09-16
    • US09711865
    • 2000-11-13
    • Hans-Georg KellerDavid Sellar
    • Hans-Georg KellerDavid Sellar
    • H04B7212
    • H04J3/0685
    • A timing device for generating and outputting a plurality of signal edges by changing signal statuses at predeterminable times. The timing device includes a cyclically addressable memory in which a plurality of time events are stored. Each time event is assigned a time value, which corresponds to a predetermined time, and a plurality of predetermined signal statuses. The timing device further includes a comparator, which compares the current count of a counter to the time value of a time event, which has just been acquired from memory. Given a match, the next time event is read from the memory. The timing device also includes an output device which outputs the predetermined signal statuses. With the timing device it is possible to freely program periodically recurring time indications by allocating memory accordingly.
    • 一种定时装置,用于通过在可预定的时间改变信号状态来产生和输出多个信号边缘。 定时装置包括其中存储多个时间事件的循环寻址存储器。 为每个时间事件分配一个对应于预定时间的时间值和多个预定信号状态。 定时装置还包括一个比较器,该比较器将当前计数器的计数与刚刚从存储器获得的时间事件的时间值进行比较。 给定一个匹配,下一次事件从内存读取。 定时装置还包括输出预定信号状态的输出装置。 利用定时装置,可以通过相应地分配存储器来周期性地定期重复执行周期性指示。
    • 7. 发明授权
    • Transmission system for transmitting and detecting the beginning of the
frame of a frame synchronized signal
    • 用于发送和检测帧同步信号的帧的开始的传输系统
    • US5671227A
    • 1997-09-23
    • US513316
    • 1995-08-10
    • Hans-Georg KellerKarl Honig
    • Hans-Georg KellerKarl Honig
    • H04J3/06H04L7/08H04L12/70H04Q11/04H04L7/00
    • H04Q11/0478H04J3/0608H04L2012/5674
    • The invention relates to a transmission system for transmitting and detecting the beginning of the frame of a frame synchronized signal, which comprises a first and a second detection circuit (1, 2) and an evaluation circuit (3). The first detection circuit (1) is provided for setting a first detection signal (D1) to a first state upon detection of a first bit sequence located at the beginning of the frame of the signal, and the second detection circuit (2) for setting a second detection signal (D2) to a first state upon detection of a second bit sequence located at a specific frame position of the signal. The evaluation circuit (3) comprises a frame counter (10) which is provided at least during the detection of the beginning of the frame, for resetting the first detection signal (D1) to an initial value after the first state has occurred, and a combining circuit (15) for forming a frame state signal (R) which has a first state only when the first state of the first detection signal (D1) occurs during the initial value, and the first state of the second detection signal (D2) occurs during a specific frame value of the frame counter (10).
    • 本发明涉及一种用于发送和检测帧同步信号的帧的开始的传输系统,其包括第一和第二检测电路(1,2)和评估电路(3)。 第一检测电路(1)被设置用于在检测到位于信号的帧的开始处的第一位序列时将第一检测信号(D1)设置为第一状态,以及用于设置第二检测电路(2) 在检测到位于信号的特定帧位置的第二位序列时,将第二检测信号(D2)转换为第一状态。 评估电路(3)包括至少在检测帧的开始期间提供的帧计数器(10),用于在第一状态发生之后将第一检测信号(D1)重置为初始值,并且 用于形成帧状态信号(R)的组合电路(15),其仅在初始值期间发生第一检测信号(D1)的第一状态时具有第一状态,并且第二检测信号(D2)的第一状态 发生在帧计数器(10)的特定帧值期间。
    • 8. 发明授权
    • Time-division multiplex transmission system
    • 时分多路传输系统
    • US5138612A
    • 1992-08-11
    • US688779
    • 1991-04-18
    • Hans-Georg KellerHans-Jurgen Reumerman
    • Hans-Georg KellerHans-Jurgen Reumerman
    • H04L12/54H04L12/70H04L12/933H04L12/937
    • H04L12/5601H04L49/106H04L49/255H04L2012/5675H04L2012/5681
    • An interconnection element for an asynchronous time-division multiplex transmission system which transmits cells supplied by auxiliary lines (14a to 14d) and destined for a trunk line (10). The element comprises cell filters (11a to 11d) coupled each to an auxiliary line. The filters pass the cells to be stored in intersection buffers (12a to 12d) coupled to each cell filter when the path identification is allocated to the trunk line for controlling the reading of the cells from the intersection buffers onto the trunk line the system includes allocation circuit comprises a chain of hierarchically structured allocation elements (13a to 13d) associated each to an intersection buffer and having each its control buffer (17a to 17d). When a cell is stored in the associated intersection buffer each allocation element stores a first status in the associated control buffer and the hierarchically lower allocation element a second status in the associated control buffers. In reverse hierarchical order each allocation element evaluates the associated control buffer and releases, when a first status is available, the allocated intersection buffer for a cell to be read out.
    • 一种用于异步时分复用传输系统的互连元件,其传输由辅助线路(14a至14d)提供并发往干线(10)的小区。 元件包括每个耦合到辅助线的单元滤波器(11a至11d)。 当路径识别被分配给中继线时,滤波器将要存储在与每个小区滤波器相连的交叉缓冲器(12a至12d)中的单元存储在一起,用于控制从交叉点缓冲区读取单元到主干线上的系统包括分配 电路包括一组分层结构的分配元件(13a至13d),每个链路分配元件(13a至13d)分别与相交缓冲器相关联,并具有每个其控制缓冲器(17a至17d)。 当小区被存储在相关联的交叉路口缓冲器中时,每个分配元件将相关控制缓冲器中的第一状态存储在相关联的控制缓冲器中,并且分层较低的分配元件存储第二状态。 以反阶层次顺序,每个分配元素评估相关联的控制缓冲器,并且当第一状态可用时释放用于要读出的单元的分配的交集缓冲器。