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1. 发明授权

US07366940B2 Multiprotocol computer bus interface adapter and method 有权
标题翻译：多协议计算机总线接口适配器和方法
公开(公告)号：US07366940B2
公开(公告)日：2008-04-29
申请号：US10990657
申请日：2004-11-17
申请人： Jennifer Y. Chiao , Gary A. Alvstad , Myles H. Wakayama
发明人： Jennifer Y. Chiao , Gary A. Alvstad , Myles H. Wakayama
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F2213/0024
摘要： A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.
摘要翻译：具有与同步器反馈延迟环耦合的预测同步器和复制延迟元件的预测时基发生器。预测时基发生器接收延迟了预定时钟延迟的时钟信号，并产生一个预测时间信号，该预测时间信号在时间上提前由复制延迟元件表示的量。复制延迟元件可以复制预定时钟延迟和预定数据延迟中的一个或两个，从而基本上使设备的关键信号路径中的相应延迟无效。复制延迟元件可以包括在输入时钟路径和输出数据路径中找到的结构的副本，这些元件包括例如电压电平移位器，缓冲器或数据锁存器，多路复用器，线元模型等。还提供了一种包含上述预测时基发生器的预测计算机总线接口适配器。这种预测接口适配器可以适应于遵守在PCI和PCI-X局部总线协议下施加的严格总线协议时序预算，并且相对于设计和制造过程以及环境操作条件的变化而言是稳健的。

2. 发明授权

US06829715B2 Multiprotocol computer bus interface adapter and method 有权
标题翻译：多协议计算机总线接口适配器和方法
公开(公告)号：US06829715B2
公开(公告)日：2004-12-07
申请号：US09865844
申请日：2001-05-25
申请人： Jennifer Y. Chiao , Gary A. Alvstad , Myles H. Wakayama
发明人： Jennifer Y. Chiao , Gary A. Alvstad , Myles H. Wakayama
IPC分类号： G06F104
CPC分类号： G06F1/10 , G06F2213/0024
摘要： A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.
摘要翻译：具有与同步器反馈延迟环耦合的预测同步器和复制延迟元件的预测时基发生器。预测时基发生器接收延迟了预定时钟延迟的时钟信号，并产生一个预测时间信号，该预测时间信号在时间上提前由复制延迟元件表示的量。复制延迟元件可以复制预定时钟延迟和预定数据延迟中的一个或两个，从而基本上使设备的关键信号路径中的相应延迟无效。复制延迟元件可以包括在输入时钟路径和输出数据路径中找到的结构的副本，这些元件包括例如电压电平移位器，缓冲器或数据锁存器，多路复用器，线元模型等。还提供了一种包含上述预测时基发生器的预测计算机总线接口适配器。这种预测接口适配器可以适应于遵守在PCI和PCI-X局部总线协议下施加的严格总线协议时序预算，并且相对于设计和制造过程以及环境操作条件的变化而言是稳健的。

3. 发明授权

US5651001A Method and apparatus for full duplex signaling 失效
标题翻译：全双工信令的方法和装置
公开(公告)号：US5651001A
公开(公告)日：1997-07-22
申请号：US363616
申请日：1994-12-22
申请人： Gary A. Alvstad , Jie Ni
发明人： Gary A. Alvstad , Jie Ni
IPC分类号： G06F13/38 , H04B1/56
CPC分类号： G06F13/385
摘要： A network transmitter device and network receiver device is described. The network transmitter device transmits a first voltage potential, a second voltage potential, a third voltage potential and a fourth voltage potential over a first pair of output lines and a second pair of output lines in response to digital signals received over a data input. The network receiver device receives network signals of a first voltage potential, a second voltage potential, a third voltage potential, a fourth voltage potential and a fifth voltage potential over a first pair of output lines and a second pair of output lines. The network receiver device transmits digital signals corresponding to the network signals.
摘要翻译：描述了网络发射机设备和网络接收机设备。响应于通过数据输入接收的数字信号，网络发射机设备在第一对输出线路和第二对输出线路上传输第一电压电位，第二电压电位，第三电压电势和第四电压电位。网络接收设备在第一对输出线和第二对输出线上接收第一电压电位，第二电压电位，第三电压电位，第四电压电位和第五电压电位的网络信号。网络接收装置发送对应于网络信号的数字信号。

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