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1. 发明申请

WO2014080292A2 INTEGRATED SENSOR FOR THE RAPID IDENTIFICATION OF BACTERIA USING ISFETS 审中-公开
标题翻译：集成传感器用于通过ISFET快速识别细菌
公开(公告)号：WO2014080292A2
公开(公告)日：2014-05-30
申请号：PCT/IB2013/003133
申请日：2013-11-22
申请人： GULAK, Glenn
发明人： NIKKHOO, Nasim , MAXWELL, Karen
IPC分类号： C12Q1/04
CPC分类号： G01N27/4145
摘要： Disclosed are methods and systems for the detection of bacteria in a sample. The methods comprises contacting the sample with an antibacterial agent and a bacteria identification sensor, and involves the permeabilization of the bacteria by the antibacterial agent, and the subsequent detection of an efflux of potassium ions using a bacteria identification sensor comprising a potassium- sensitive ISFET. Also disclosed are bacteria identification sensor comprising a potassium-sensitive ISFET useful in the practice of the disclosed methods.
摘要翻译：公开了用于检测样品中的细菌的方法和系统。该方法包括使样品与抗菌剂和细菌鉴定传感器接触，并且涉及细菌被抗细菌剂透化，并且随后使用包含钾敏感的ISFET的细菌鉴定传感器检测钾离子的流出。还公开了包含在实施所公开的方法中有用的对钾敏感的ISFET的细菌识别传感器。

2. 发明申请

WO2014080292A3 INTEGRATED SENSOR FOR THE RAPID IDENTIFICATION OF BACTERIA USING ISFETS 审中-公开
标题翻译：使用ISFET快速鉴定细菌的综合传感器
公开(公告)号：WO2014080292A3
公开(公告)日：2014-10-30
申请号：PCT/IB2013003133
申请日：2013-11-22
申请人： GULAK GLENN
发明人： NIKKHOO NASIM , MAXWELL KAREN
IPC分类号： C12Q1/04 , C12M1/34 , C12Q1/18 , G01N27/403 , G01N27/414 , G01N33/48
CPC分类号： G01N27/4145
摘要： Disclosed are methods and systems for the detection of bacteria in a sample. The methods comprises contacting the sample with an antibacterial agent and a bacteria identification sensor, and involves the permeabilization of the bacteria by the antibacterial agent, and the subsequent detection of an efflux of potassium ions using a bacteria identification sensor comprising a potassium- sensitive ISFET. Also disclosed are bacteria identification sensor comprising a potassium-sensitive ISFET useful in the practice of the disclosed methods.
摘要翻译：公开了用于检测样品中的细菌的方法和系统。所述方法包括使样品与抗菌剂和细菌识别传感器接触，并且涉及通过抗菌剂使细菌透化，以及随后使用包含钾敏感型ISFET的细菌识别传感器检测钾离子的流出。还公开了细菌鉴定传感器，其包括在实践所公开的方法中有用的钾敏感的ISFET。

3. 发明申请

WO2003088504A1 PROCEDE DE CODAGE ET/OU DE DECODAGE DE CODES CORRECTEURS D'ERREURS, DISPOSITIFS ET SIGNAL CORRESPONDANTS. 审中-公开
标题翻译：用于编码和/或解码错误校正码的方法，以及相应的设备和信号
公开(公告)号：WO2003088504A1
公开(公告)日：2003-10-23
申请号：PCT/FR2003/001188
申请日：2003-04-14
申请人： UNIVERSITE DE BRETAGNE SUD , BOUTILLON, Emmanuel , GULAK, Glenn , GAUDET, Vincent , GNAEDIG, David
发明人： BOUTILLON, Emmanuel , GULAK, Glenn , GAUDET, Vincent , GNAEDIG, David
IPC分类号： H03M13/29
CPC分类号： H03M13/1137 , G11B2020/10944 , H03M13/2771 , H03M13/2957 , H03M13/6566
摘要： L'invention concerne un procédé de décodage de code correcteur d'erreurs, du type associant un bloc de données décodé à des données codées selon un code global comprenant au moins deux sous-caves constituants (Ri), un graphe bipartite irrégulier étant associé au code global, le procédé de décodage étant itératif, un bloc de données à décoder étant réparti dans une pluralité de bancs mémoires disjoints (Mi), adressages indépendamment, le procédé comprenant, en outre à chaque itération , une étape d'alimentation en parallèle d'au moins deux décodeurs (671, 672, 67i, 67P) correspondant chacun respectivement à au moins un des sous-caves, par des données à décoder, des données à décoder étant extraites en parallèle d'au moins deux des bancs mémoires (Mi) pour alimenter autant de décodeurs, et chacun des décodeurs étant alimenté séquentiellement par les données à décoder lui correspondant. L'invention concerne également un procédé de codage, des dispositifs de codage/décodage et un signal correspondants.
摘要翻译：本发明涉及一种解码纠错码的方法，其中根据包括至少两个子码（Ri）的全局码，解码数据块与编码数据相关联。根据本发明，不规则二分图与全局代码相关联，解码方法是迭代的，并且要被解码的数据块被分布在可以独立寻址的多个不相交的存储体（Mi）之间。本发明的方法还包括在每次迭代时，根据要解码的数据，并行地馈送至少两个解码器（671,672,67i，67P），其分别对应于至少一个子代码，从至少两个存储体（Mi）并行提取要解码的数据，以便馈送相同量的解码器，并且每个解码器依次馈送与其对应的要解码的数据。本发明还涉及对应的编码方法，对应的编码/解码装置和相应的信号。

4. 发明申请

WO2014111817A3 METHOD AND SYSTEM FOR MAXIMUM ACHIEVABLE EFFICIENCY IN NEAR-FIELD COUPLED WIRELESS POWER TRANSFER SYSTEMS 审中-公开
标题翻译：近场耦合无线电力传输系统中最大可达效率的方法和系统
公开(公告)号：WO2014111817A3
公开(公告)日：2014-12-04
申请号：PCT/IB2014000676
申请日：2014-01-06
申请人： GULAK GLENN
发明人： GULAK GLENN , ZARGHAM MEYSAM
IPC分类号： H02J17/00 , H01F5/00 , H03H7/40 , H05K1/16
CPC分类号： H02J50/10 , G01R27/02 , G01R33/16 , H01F27/2804 , H01F38/14 , H02J5/005 , H02J7/025
摘要： Methods and systems for maximum efficiency achievable in near-field coupled wireless power transfer systems are disclosed and may include configuring coil geometry, independently of load impedance and source impedance, for a transmit (Tx) coil and a receive (Rx) coil based on a media expected to be between the coils during operation. A desired susceptance and conductance may be determined and an impedance of an amplifier for the Tx coil may be configured based on the determined susceptance and conductance. A load impedance for the Rx coil may be configured based on the determined susceptance and conductance. A matching network may be coupled to the amplifier. The Rx coil may be integrated on a complementary metal-oxide semiconductor (CMOS) chip. One or more matching networks may be integrated on the CMOS chip for the configuring of the load impedance for the Rx coil.
摘要翻译：公开了用于在近场耦合无线功率传输系统中实现的最大效率的方法和系统，并且可以包括基于一个发射（Tx）线圈和接收（Rx）线圈来独立于负载阻抗和源阻抗配置线圈几何形状介质在操作期间预计会在线圈之间。可以确定期望的电纳和电导，并且可以基于确定的电纳和电导来配置用于Tx线圈的放大器的阻抗。 Rx线圈的负载阻抗可以基于确定的电纳和电导来配置。匹配网络可以耦合到放大器。 Rx线圈可以集成在互补金属氧化物半导体（CMOS）芯片上。一个或多个匹配网络可以集成在CMOS芯片上，用于配置Rx线圈的负载阻抗。

5. 发明申请

WO2012158223A1 METHOD AND APPARATUS FOR MEMORY POWER AND/OR AREA REDUCTION 审中-公开
标题翻译：用于存储功率和/或区域减少的方法和装置
公开(公告)号：WO2012158223A1
公开(公告)日：2012-11-22
申请号：PCT/US2012/023977
申请日：2012-02-06
申请人： MAXLINEAR, INC. , LING, Curtis , SMOLYAKOV, Vadim , GALLAGHER, Timothy , GULAK, Glenn
发明人： LING, Curtis , SMOLYAKOV, Vadim , GALLAGHER, Timothy
IPC分类号： G06F11/00
CPC分类号： G11C5/144 , G06F11/1048 , G11C5/14 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage V mem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
摘要翻译：一种用于存储器功率和/或面积减小的方法和装置。可以扫描存储器单元阵列以检测阵列中的故障存储器单元（如果有的话）。可以基于扫描的结果并且基于存储器单元阵列中的一个或多个的灵敏度系数来控制施加到存储器单元阵列的电源电压Vmem。灵敏度系数可以指示存储器单元阵列中的一个或多个存在故障的影响可能对于将数据读取和写入存储器阵列的设备的性能有影响。附加地或替代地，存储器单元的物理尺寸可以基于灵敏度系数和/或基于可以在存储器单元阵列中容忍的故障存储器单元的数量来确定。

6. 发明专利

SG195026A1 METHOD AND APPARATUS FOR MEMORY POWER AND/OR AREA REDUCTION 未知
公开(公告)号：SG195026A1
公开(公告)日：2013-12-30
申请号：SG2013085220
申请日：2012-02-06
申请人： MAXLINEAR INC , GULAK GLENN
发明人： LING CURTIS , SMOLYAKOV VADIM , GALLAGHER TIMOTHY
摘要： A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

7. 发明申请

WO2014111817A2 METHOD AND SYSTEM FOR MAXIMUM ACHIEVABLE EFFICIENCY IN NEAR-FIELD COUPLED WIRELESS POWER TRANSFER SYSTEMS 审中-公开
标题翻译：近场无线电力传输系统中最大可实现效率的方法与系统
公开(公告)号：WO2014111817A2
公开(公告)日：2014-07-24
申请号：PCT/IB2014/000676
申请日：2014-01-06
申请人： GULAK, Glenn
发明人： GULAK, Glenn , ZARGHAM, Meysam
CPC分类号： H02J50/10 , G01R27/02 , G01R33/16 , H01F27/2804 , H01F38/14 , H02J5/005 , H02J7/025
摘要： Methods and systems for maximum efficiency achievable in near-field coupled wireless power transfer systems are disclosed and may include configuring coil geometry, independently of load impedance and source impedance, for a transmit (Tx) coil and a receive (Rx) coil based on a media expected to be between the coils during operation. A desired susceptance and conductance may be determined and an impedance of an amplifier for the Tx coil may be configured based on the determined susceptance and conductance. A load impedance for the Rx coil may be configured based on the determined susceptance and conductance. A matching network may be coupled to the amplifier. The Rx coil may be integrated on a complementary metal-oxide semiconductor (CMOS) chip. One or more matching networks may be integrated on the CMOS chip for the configuring of the load impedance for the Rx coil.
摘要翻译：公开了在近场耦合无线电力传输系统中可实现的用于最大效率的方法和系统，并且可以包括针对发射（Tx）线圈和接收（Rx）线圈来配置线圈几何，独立于负载阻抗和源阻抗，基于媒体期望在运营期间在线圈之间。可以基于确定的电纳和电导来确定期望的电纳和电导，并且可以根据确定的电纳和电导来配置用于Tx线圈的放大器的阻抗。可以基于所确定的电纳和电导来配置Rx线圈的负载阻抗。匹配网络可以耦合到放大器。 Rx线圈可以集成在互补金属氧化物半导体（CMOS）芯片上。一个或多个匹配网络可以集成在CMOS芯片上用于配置Rx线圈的负载阻抗。

8. 发明申请

WO2012158222A1 METHOD AND APPARATUS FOR MEMORY FAULT TOLERANCE 审中-公开
标题翻译：用于记忆容忍度的方法和装置
公开(公告)号：WO2012158222A1
公开(公告)日：2012-11-22
申请号：PCT/US2012/023975
申请日：2012-02-06
申请人： MAXLINEAR, INC. , LING, Curtis , SMOLYAKOV, Vadim , GALLAGHER, Timothy , GULAK, Glenn
发明人： LING, Curtis , SMOLYAKOV, Vadim , GALLAGHER, Timothy , GULAK, Glenn
IPC分类号： G11C8/00
CPC分类号： G11C29/00 , G06F11/1048 , G11C7/1006 , G11C29/04 , G11C29/76 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.
摘要翻译：可以使用多条数据线和多条位线来写入和/或从存储器单元阵列读取。开关元件可以在多条数据线与多条位线之间的不同映射中进行选择。阵列可以例如由N个存储器单元组成，多个位线可以由N个位线组成，并且多个数据线可以由N个数据线组成，其中N是大于1的整数。对于写入至少部分地基于数据块对存储器单元阵列中的故障存储器单元的敏感度来控制开关元件的配置，其中将数据块写入阵列的操作。

9. 发明申请

WO2011150428A1 METHOD AND SYSTEM FOR A LOW-COMPLEXITY SOFT-OUTPUT MIMO DETECTION 审中-公开
标题翻译：用于低复杂度软输出MIMO检测的方法和系统
公开(公告)号：WO2011150428A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/038642
申请日：2011-05-31
申请人： MAXLINEAR, INC. , PATEL, Dimpesh , SHABANY, Mahdi , GULAK, Glenn
发明人： PATEL, Dimpesh , SHABANY, Mahdi , GULAK, Glenn
IPC分类号： H04L27/06
CPC分类号： H04B7/0456 , H04L25/03203
摘要： An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2N T 1 (N T = number of transmit antennas) on-demand to only 2K1 lowest Partial Euclidean Distance (PED) paths at last tree level 2N T . The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.
摘要翻译：用于软输出K-Best MIMO检测的方法包括计算用于发送位的估计符号向量和对数似然比（LLR）值。该方法包括相关的丢弃路径选择过程，最后一阶段按需扩展过程以及松弛的LLR计算过程。相关丢弃路径选择过程包括分析每个中间树级别的K-Best路径和丢弃路径，并且仅选择那些被丢弃的路径用于进一步处理，这将有助于至少一个发送位的LLR计算。最后阶段按需扩展过程包括根据需要在树级别2NT1（NT =发射天线数）上将K路径扩展到最后树级别2NT处的仅2K1最小部分欧几里德距离（PED）路径。松弛的LLR计算方案包括通过假设丢弃的路径PED大于或等于K-最佳路径PED来近似LLR计算。

10. 发明申请

WO2010135745A1 SIGNAL PROCESSING BLOCK FOR A RECEIVER IN WIRELESS COMMUNICATION 审中-公开
标题翻译：无线通信接收机的信号处理块
公开(公告)号：WO2010135745A1
公开(公告)日：2010-11-25
申请号：PCT/US2010/035989
申请日：2010-05-24
申请人： MAXLINEAR, INC. , PATEL, Dimpesh , GULAK, Glenn , SHABANY, Mahdi
发明人： PATEL, Dimpesh , GULAK, Glenn , SHABANY, Mahdi
IPC分类号： H01Q21/00
CPC分类号： H01Q23/00 , G06F17/16 , H01Q21/28
摘要： A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented (290) that uses un-rolled pipelined CORDIC processors (245a to 245d) iteratively to improve throughput and resource utilization, while reducing the gate count.
摘要翻译：用于在无线通信的接收机中计算输入信号的QRD处理器依赖于多维Givens旋转，Householder反射和常规二维（2D）Givens旋转的组合，用于计算矩阵的QRD。所提出的技术整合了众议院反思的多维湮灭能力的好处加上常规2D Givens旋转的低复杂度性质。这种集成通过首先减少所需的旋转操作数量，然后通过使其并行执行来增加吞吐量并降低硬件复杂性。提出了一种流水线架构（290），它可以迭代地使用未压缩的流水线CORDIC处理器（245a到245d）来提高吞吐量和资源利用率，同时减少门数。

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