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    • 1. 发明申请
    • SYSTEM AND METHOD FOR PERFORMING AN OPTIMIZED DISCRETE WALSH TRANSFORM
    • 用于执行优化的离散沃尔夫变换的系统和方法
    • WO2008070315A3
    • 2008-08-21
    • PCT/US2007082204
    • 2007-10-23
    • L3 COMM INTEGRATED SYSTEMS LPGARCIA ROGER ERICMORTON ROBERT RYANSTOPCZYNSKI DENNIS J
    • GARCIA ROGER ERICMORTON ROBERT RYANSTOPCZYNSKI DENNIS J
    • G06F17/14
    • G06F17/145
    • A circuit performs a discrete Walsh transform that comprises a first memory component, an adder, a subtracter, a second memory component, and a controller. In each of a plurality of stages, the controller enables the first memory component to communicate each of a plurality of pairs of values stored therein to the adder and to the subtracter. The controller enables the second memory component to store each of a plurality of results from the adder and the subtracter and to communicate the stored results to the first memory component for use in a subsequent stage. In the subsequent stage, the controller enables the first memory component to communicate to the adder and to the subtracter a plurality of new pairs of data values consisting first of the add results and then the subtract results from the previous stage in the order they were generated
    • 电路执行包括第一存储器组件,加法器,减法器,第二存储器组件和控制器的离散沃尔什变换。 在多级中的每一级中,控制器使得第一存储器组件能够将存储在其中的多对值中的每一个传送到加法器和减法器。 所述控制器使得所述第二存储器组件能够存储来自所述加法器和所述减法器的多个结果中的每一个,并且将所存储的结果传送到所述第一存储器组件以用于后续阶段。 在后续阶段,控制器使得第一存储器组件能够与加法器和减法器通信,将多个新的数据值对组合成第一个加法结果,然后按照它们生成的顺序从前一级减去结果
    • 4. 发明申请
    • SYSTEM AND METHOD FOR PERFORMING AN OPTIMIZED DISCRETE WALSH TRANSFORM
    • 用于执行优化的离散沃尔夫变换的系统和方法
    • WO2008070315A2
    • 2008-06-12
    • PCT/US2007/082204
    • 2007-10-23
    • L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.GARCIA, Roger, EricMORTON, Robert, RyanSTOPCZYNSKI, Dennis, J.
    • GARCIA, Roger, EricMORTON, Robert, RyanSTOPCZYNSKI, Dennis, J.
    • G06F7/50
    • G06F17/145
    • A circuit (26) performs a discrete Walsh transform using a reduced set of arithmetic operators. The circuit (26) comprises a first memory component (32), an adder (36), a subtractor (38), a second memory component (40), and a controller (52). In each of a plurality of stages, the controller (52) enables the first memory component (32) to communicate each of a plurality of pairs of values stored therein to the adder (36) and to the subtractor (38). The controller (52) enables the second memory component (40) to store each of a plurality of results from the adder (36) and the subtractor (38) and to communicate the stored results to the first memory component (32) for use in a subsequent stage. In the subsequent stage, the controller (52) enables the first memory component (32) to communicate to the adder (36) and to the subtractor (38) a plurality of new pairs of data values consisting first of the add results from the previous stage in the order they were generated and then the subtract results in the order they were generated.
    • 电路(26)使用减少的算术运算符进行离散沃尔什变换。 电路(26)包括第一存储器组件(32),加法器(36),减法器(38),第二存储器组件(40)和控制器(52)。 在多级中的每一级中,控制器(52)使得第一存储器组件(32)能够将存储在其中的多对值中的每一个传送到加法器(36)和减法器(38)。 控制器(52)使得第二存储器组件(40)能够存储来自加法器(36)和减法器(38)的多个结果中的每一个,并将存储的结果传送到第一存储器组件(32)以用于 后续阶段 在随后的阶段中,控制器52使第一存储器组件32能够与加法器36和减法器38通信多个新的数据值对,这些数据值由先前的 按照产生的顺序进行阶段,然后按照生成的顺序减去结果。