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1. 发明授权

US06425023B1 Method and system for gathering and buffering sequential data for a transaction comprising multiple data access requests 失效
标题翻译：用于收集和缓冲包含多个数据访问请求的事务的顺序数据的方法和系统
公开(公告)号：US06425023B1
公开(公告)日：2002-07-23
申请号：US09275603
申请日：1999-03-24
申请人： Gary William Batchelor , Carl Evan Jones , Dell Patrick Leabo , Robert Earl Medlin , Forrest Lee Wade
发明人： Gary William Batchelor , Carl Evan Jones , Dell Patrick Leabo , Robert Earl Medlin , Forrest Lee Wade
IPC分类号： G06F1314
CPC分类号： G06F13/4027
摘要： Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent. In a similar manner, in delayed write operations, the write data may also be gathered from several write operations and assembled into an address boundary-aligned block of write data before the bridge circuit forwards the write data to the target device.
摘要翻译：公开了一种用于通过总线处理读和写交易的桥接系统，其中在优选实施例中，通过辅助总线在多个单独的读取操作中从目标设备获得的连续读取数据可以由桥梁收集并组装成更大的在通过主总线将数据转发到请求代理之前的数据块。因此，可以增加在主总线上传输读取数据的最佳地址边界对准突发，相反地，可以减少通过主总线的分级，非对齐读取数据的传输。由于每个代理被分配特定的缓冲区，读取数据可以在分配的桥接缓冲器中同时收集，而不会由一个代理导致对不同代理收集的数据的刷新的读取请求。以类似的方式，在延迟写入操作中，也可以从桥接电路将写入数据转发到目标设备之前，从多个写入操作中收集写入数据并将其组合成写入数据的地址边界对齐块。

2. 发明授权

US06502157B1 Method and system for perfetching data in a bridge system 有权
标题翻译：在桥梁系统中提供数据的方法和系统
公开(公告)号：US06502157B1
公开(公告)日：2002-12-31
申请号：US09275857
申请日：1999-03-24
申请人： Gary William Batchelor , Carl Evan Jones , Forrest Lee Wade
发明人： Gary William Batchelor , Carl Evan Jones , Forrest Lee Wade
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： Disclosed is a bridge system and method for prefetching data to return to a read request from an agent. The bridge system includes at least one memory device including a counter indicating a number of prefetch operations to perform to prefetch all the requested data, a first buffer capable of storing prefetch requests, and a second buffer capable of storing read data. Control logic implemented in the bridge system includes means for queuing at least one prefetch operation in the first buffer while the counter is greater than zero. The control logic then executes a queued prefetch operation, subsequently receives the prefetched data, and stores the prefetched data in the second buffer. The stored prefetched data is returned to the requesting agent.
摘要翻译：公开了一种用于预取数据以从代理返回到读请求的桥系统和方法。桥接系统包括至少一个存储器装置，其包括指示预取数量的预取操作以预取所有所请求的数据的计数器，能够存储预取请求的第一缓冲器和能够存储读取数据的第二缓冲器。在桥系统中实现的控制逻辑包括用于在计数器大于零时在第一缓冲器中排队至少一个预取操作的装置。控制逻辑然后执行排队预取操作，随后接收预取数据，并将预取数据存储在第二缓冲器中。存储的预取数据被返回给请求代理。

3. 发明授权

US06324621B2 Data caching with a partially compressed cache 失效
标题翻译：使用部分压缩的缓存进行数据缓存
公开(公告)号：US06324621B2
公开(公告)日：2001-11-27
申请号：US09090028
申请日：1998-06-10
申请人： Shanker Singh , Joe-Ming Cheng , Brent Cameron Beardsley , Dell Patrick Leabo , Forrest Lee Wade , Michael Thomas Benhase , Marc Ethan Goldfeder
发明人： Shanker Singh , Joe-Ming Cheng , Brent Cameron Beardsley , Dell Patrick Leabo , Forrest Lee Wade , Michael Thomas Benhase , Marc Ethan Goldfeder
IPC分类号： G06F1200
CPC分类号： G06F12/0802 , G06F12/0871 , G06F12/0897 , G06F12/127 , G06F2212/401
摘要： Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.
摘要翻译：用于缓存存储数据的方面包括对存储高速缓存进行划分以包括压缩数据分区和未压缩数据分区，以及调整所选择的性能特征的压缩数据分区和未压缩数据分区的大小。具有与存储系统通信的主机系统的数据处理系统中的数据缓存系统方面包括至少一个存储设备和至少一个部分压缩的高速缓存。所述至少一个部分压缩缓存还包括未压缩分区和压缩分区，其中所述压缩分区至少存储来自未压缩分区的受害数据单元。

4. 发明授权

US6112311A Bridge failover system 失效
标题翻译：桥接故障转移系统
公开(公告)号：US6112311A
公开(公告)日：2000-08-29
申请号：US26620
申请日：1998-02-20
申请人： Brent Cameron Beardsley , Carl Evan Jones , Forrest Lee Wade
发明人： Brent Cameron Beardsley , Carl Evan Jones , Forrest Lee Wade
IPC分类号： G06F11/20 , G06F13/40 , H04L12/46 , G06F11/00
CPC分类号： G06F11/2005 , G06F13/4027 , H04L12/462 , G06F11/2007
摘要： Disclosed is a system for communication among a device, a first processor, and a second processor. One of a first data path and second data path is configured. The first data path comprises a bus, such as a local PCI bus, a first remote bridge, and a first local bridge. The bridges may be comprised of PCI to PCI bridges. After configuring the first data path, the device communicates to the first processor by communicating data through the bus to the first remote bridge. The first remote bridge transmits the data to the first local bridge and the first local bridge transmits the data to the first processor. The second data path comprises the bus, a second remote bridge, and a second local bridge. After configuring the second data path, the device communicates to the second processor by communicating data through the bus to the second remote bridge. The second remote bridge transmits the data to the second local bridge and the second local bridge transmits the data to the second processor.
摘要翻译：公开了一种用于设备，第一处理器和第二处理器之间的通信的系统。配置第一数据路径和第二数据路径之一。第一数据路径包括总线，例如本地PCI总线，第一远程桥和第一局部桥。桥可以由PCI到PCI桥组成。在配置第一数据路径之后，设备通过总线将数据传送到第一远程桥与第一处理器通信。第一个远程桥将数据发送到第一个本地网桥，第一个本地桥将数据传输到第一个处理器。第二数据路径包括总线，第二远程桥和第二局部桥。在配置第二数据路径之后，设备通过总线将数据传送到第二远程桥与第二处理器进行通信。第二远程桥将数据发送到第二本地网桥，而第二本地桥将数据传送到第二处理器。

5. 发明授权

US06286074B1 Method and system for reading prefetched data across a bridge system 失效
标题翻译：在桥系统上读取预取数据的方法和系统
公开(公告)号：US06286074B1
公开(公告)日：2001-09-04
申请号：US09275610
申请日：1999-03-24
申请人： Gary William Batchelor , Brent Cameron Beardsley , Matthew Joseph Kalos , Forrest Lee Wade
发明人： Gary William Batchelor , Brent Cameron Beardsley , Matthew Joseph Kalos , Forrest Lee Wade
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： Disclosed is a bridge system for processing read transactions over a bus in which in a preferred embodiment prefetched data stored in a buffer is not discarded if the address of the requested read does not match the beginning address of the prefetched data. Instead, the bridge system skips to the next address of the prefetched data stored in the buffer and compares that address to the address of the read request to determine if a match exists. If the requested read address does match the next prefetched data address, the prefetched data starting at that next address is read out and forwarded to the requesting agent. Alternatively, if there is not a match, the bridge skips again to the next address and continues checking for a match until either the prefetched data is exhausted or another predetermined limit has been reached. In this manner, many unnecessary data reads of data already prefetched in the buffer may be avoided.
摘要翻译：公开了一种用于通过总线处理读取事务的桥接系统，其中在优选实施例中，如果所请求的读取的地址与预取数据的起始地址不匹配，则不会丢弃存储在缓冲器中的预取数据。相反，桥接系统跳过存储在缓冲器中的预取数据的下一个地址，并将该地址与读取请求的地址进行比较，以确定是否存在匹配。如果所请求的读取地址与下一个预取数据地址匹配，则从该下一个地址开始的预取数据被读出并转发给请求代理。或者，如果不匹配，桥接器再次跳到下一个地址，并继续检查匹配，直到预取的数据被耗尽或达到了另一个预定的限制。以这种方式，可以避免在缓冲器中预取的数据的许多不必要的数据读取。

6. 发明授权

US06449678B1 Method and system for multiple read/write transactions across a bridge system 失效
标题翻译：跨桥系统进行多次读/写交易的方法和系统
公开(公告)号：US06449678B1
公开(公告)日：2002-09-10
申请号：US09275470
申请日：1999-03-24
申请人： Gary William Batchelor , Russell Lee Ellison , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Forrest Lee Wade , Juan Antonio Yanes
发明人： Gary William Batchelor , Russell Lee Ellison , Carl Evan Jones , Robert Earl Medlin , Belayneh Tafesse , Forrest Lee Wade , Juan Antonio Yanes
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.
摘要翻译：公开了一种用于通过总线处理来自多个代理的读/写交易的系统。该桥包括与桥接通信的每个代理的至少一个请求缓冲器。代理的请求缓冲区缓冲来自该代理的事务。桥接器还包括与桥接器通信的每个代理的返回缓冲器。代理缓冲区缓冲区返回与事务相关的数据。地址转换电路与总线通信，请求和返回缓冲器。地址转换电路定位请求缓冲器以对事务进行排队，使得事务存储在与发起事务的代理相对应的请求缓冲器中。此外，地址转换电路将用于读取事务的读取返回数据存储在与发起事务的代理相对应的返回缓冲器中。

7. 发明授权

US6035347A Secure store implementation on common platform storage subsystem (CPSS) by storing write data in non-volatile buffer 失效
标题翻译：通过将写入数据存储在非易失性缓冲区中，在通用平台存储子系统（CPSS）上实现安全存储
公开(公告)号：US6035347A
公开(公告)日：2000-03-07
申请号：US994312
申请日：1997-12-19
申请人： Brent Cameron Beardsley , Michael Thomas Benhase , Forrest Lee Wade
发明人： Brent Cameron Beardsley , Michael Thomas Benhase , Forrest Lee Wade
IPC分类号： G06F11/14 , C06F11/10
CPC分类号： G06F11/1441
摘要： A data storage system and method for securely storing data includes (a) a host CPU; (b) a non-volatile storage (NVS) memory for storing data; (c) a processor, the processor being coupled to the host CPU and the NVS memory and monitoring availability of space in the NVS memory and in a non-volatile buffer (NV-Buffer); and (d) the NV-Buffer, the NV-Buffer being coupled to the host CPU, the NVS memory, and the processor, upon receiving a request to write data into the NVS memory, the host CPU storing data to be transferred to the NVS memory into the NV-Buffer, and upon receiving a confirmation message that data of a write operation to the NV-Buffer is committed, the NV-Buffer transferring the data to the NVS memory. The NVS memory includes a fast dump space for storing data transferred from the NV-Buffer when a main power is down and for restoring back data from the NVS memory to the NV-Buffer when the power is up. The NV-Buffer is a fast drain buffer and is equipped with a backup power source sufficient to hold up a power needed to transfer the data when the power is down.
摘要翻译：用于安全地存储数据的数据存储系统和方法包括：（a）主机CPU; （b）用于存储数据的非易失性存储（NVS）存储器; （c）处理器，所述处理器耦合到所述主机CPU和所述NVS存储器并且监视所述NVS存储器和非易失性缓冲器（NV缓冲器）中的空间的可用性; 和（d）NV缓冲器，NV缓冲器在接收到将数据写入NVS存储器的请求时，耦合到主机CPU，NVS存储器和处理器，主机CPU存储要传送到 NVS存储器进入NV-Buffer，并且在接收到对NV-Buffer的写入操作的数据提交的确认消息时，NV-Buffer将数据传送到NVS存储器。 NVS存储器包括快速转储空间，用于在主电源关闭时存储从NV-Buffer传输的数据，并在电源关闭时将数据从NVS存储器恢复到NV缓冲区。 NV-Buffer是一个快速漏极缓冲器，并配有备用电源，足以在掉电时保持传输数据所需的电力。

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