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1. 发明授权

US08495532B2 Systems and methods for creating frequency-dependent RC extraction netlist 有权
标题翻译：用于创建频率依赖的RC提取网表的系统和方法
公开(公告)号：US08495532B2
公开(公告)日：2013-07-23
申请号：US13076649
申请日：2011-03-31
申请人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265
摘要： A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.
摘要翻译：一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

2. 发明申请

US20120297092A1 MANAGING DATA MOVEMENT IN A CELL BROADBAND ENGINE PROCESSOR 失效
标题翻译：在小区宽带发动机处理器中管理数据运动
公开(公告)号：US20120297092A1
公开(公告)日：2012-11-22
申请号：US13557014
申请日：2012-07-24
申请人： Zheng Wang , Liang Chen , Wenjun Wang , Feng Kuan
发明人： Zheng Wang , Liang Chen , Wenjun Wang , Feng Kuan
IPC分类号： G06F3/00
CPC分类号： G06F15/16
摘要： A cell broadband engine processor includes memory, a power processing element (PPE) coupled with the memory, and a plurality of synergistic processing elements. The PPE creates a SPE as a computing SPE for an application. The PPE determines idles ones of the plurality of SPEs, and creates a managing SPE from one of the idle SPEs. Each of the plurality of SPEs is associated with a local storage. The managing SPE informs the computing SPE of a starting effective address of the local storage of the managing SPE and an effective address for a command queue. The managing SPE manages movement of data associated with computing of the computing SPE based on one or more commands associated with the application. A computing SPE sends the one or more commands to the managing SPE for insertion into the command queue.
摘要翻译：小区宽带引擎处理器包括存储器，与存储器耦合的功率处理元件（PPE）以及多个协同处理元件。 PPE创建一个SPE作为应用程序的计算SPE。 PPE确定多个SPE中的空闲的SPE，并且从空闲SPE之一创建管理SPE。多个SPE中的每一个与本地存储器相关联。管理SPE将计算SPE通知管理SPE的本地存储的起始有效地址和命令队列的有效地址。管理SPE基于与应用相关联的一个或多个命令来管理与计算SPE的计算相关联的数据的移动。计算SPE将一个或多个命令发送到管理SPE以插入到命令队列中。

3. 发明申请

US20120254811A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT RC EXTRACTION NETLIST 有权
标题翻译：用于创建频率依赖性RC提取网络列表的系统和方法
公开(公告)号：US20120254811A1
公开(公告)日：2012-10-04
申请号：US13076649
申请日：2011-03-31
申请人： Ke-Ying SU , Ching-Shun YANG , Jui-Feng KUAN , Hsiao-Shu CHAO , Yi-Kan CHENG
发明人： Ke-Ying SU , Ching-Shun YANG , Jui-Feng KUAN , Hsiao-Shu CHAO , Yi-Kan CHENG
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265
摘要： A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.
摘要翻译：一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

4. 发明授权

US08252489B2 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08252489B2
公开(公告)日：2012-08-28
申请号：US13167905
申请日：2011-06-24
申请人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
发明人： Ke-Ying Su , Chung-Hsing Wang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G06F17/5081 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。模拟最坏情况性能的步骤包括计算与掩模移位相对应的电容值，并且使用高阶方程或分段方程计算电容值。

5. 发明授权

US06903644B2 Inductor device having improved quality factor 有权
标题翻译：具有改善品质因数的电感器件
公开(公告)号：US06903644B2
公开(公告)日：2005-06-07
申请号：US10628150
申请日：2003-07-28
申请人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
发明人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
IPC分类号： H01F17/00 , H01L23/522 , H01F5/00
CPC分类号： H01L23/5227 , H01F17/0013 , H01F2017/008 , H01L2924/0002 , H01L2924/00
摘要： An inductor device including a first coil conductor (310) and a second coil conductor (510), the first coil conductor (310) being located over a substrate (120) and having a first pattern and a first conductivity, and the second coil conductor (510) being located on a substantial portion of the first coil conductor (310), having a second pattern substantially conforming to the first pattern, and having a second conductivity substantially greater than the first conductivity.
摘要翻译：一种包括第一线圈导体（310）和第二线圈导体（510）的电感器件，所述第一线圈导体（310）位于衬底（120）之上并且具有第一图案和第一导电性，并且所述第二线圈导体（510）位于所述第一线圈导体（310）的主要部分上，具有基本上符合所述第一图案的第二图案，并且具有基本上大于所述第一导电性的第二导电。

6. 发明申请

US20050024176A1 Inductor device having improved quality factor 有权
标题翻译：具有改善品质因数的电感器件
公开(公告)号：US20050024176A1
公开(公告)日：2005-02-03
申请号：US10628150
申请日：2003-07-28
申请人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
发明人： Sung-Hsiung Wang , Shuo-Mao Chen , Heng-Ming Hsu , Jui-Feng Kuan , Chih-Ping Chao , Chih-Hsien Lin
IPC分类号： H01F17/00 , H01L23/522 , H01F5/00
CPC分类号： H01L23/5227 , H01F17/0013 , H01F2017/008 , H01L2924/0002 , H01L2924/00
摘要： An inductor device including a first coil conductor (310) and a second coil conductor (510), the first coil conductor (310) being located over a substrate (120) and having a first pattern and a first conductivity, and the second coil conductor (510) being located on a substantial portion of the first coil conductor (310), having a second pattern substantially conforming to the first pattern, and having a second conductivity substantially greater than the first conductivity.
摘要翻译：一种包括第一线圈导体（310）和第二线圈导体（510）的电感器件，所述第一线圈导体（310）位于衬底（120）之上并且具有第一图案和第一导电性，并且所述第二线圈导体（510）位于所述第一线圈导体（310）的主要部分上，具有基本上符合所述第一图案的第二图案，并且具有基本上大于所述第一导电性的第二导电。

7. 发明申请

US20130246986A1 METHOD OF CIRCUIT DESIGN YIELD ANALYSIS 有权
标题翻译：电路设计分析方法
公开(公告)号：US20130246986A1
公开(公告)日：2013-09-19
申请号：US13535709
申请日：2012-06-28
申请人： Chin-Cheng KUO , Wei-Yi HU , Jui-Feng KUAN , Yi-Kan CHENG
发明人： Chin-Cheng KUO , Wei-Yi HU , Jui-Feng KUAN , Yi-Kan CHENG
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.
摘要翻译：一种方法包括（a）产生一组样本，每个样本表示相应的一组半导体制造工艺变化值; （b）基于与每个样本相对应的半导体制造工艺变化值的集合的概率来选择该组样本的第一子集; （c）在不执行蒙特卡罗模拟的情况下，基于所述一组样本和所述第一子集的相对大小来估计半导体产品的屈服度量; 以及（d）如果估计的收益率测量低于规格收益率值，则输出设计修改适当的指示。

8. 发明申请

US20130014070A1 SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST 有权
标题翻译：用于创建频率依赖的网络列表的系统和方法
公开(公告)号：US20130014070A1
公开(公告)日：2013-01-10
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying SU , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

9. 发明申请

US20080269362A1 Recycled thermosetting flour composites and method for preparing the same 审中-公开
标题翻译：回收热固性面粉复合材料及其制备方法
公开(公告)号：US20080269362A1
公开(公告)日：2008-10-30
申请号：US12070527
申请日：2008-02-19
申请人： Chen-Feng Kuan , Chia-Hsun Chen , Min-Chi Chung , Hsu-Chiang Kuan , Kun-Chang Lin , Hsin-Chin Peng
发明人： Chen-Feng Kuan , Chia-Hsun Chen , Min-Chi Chung , Hsu-Chiang Kuan , Kun-Chang Lin , Hsin-Chin Peng
IPC分类号： C08J11/04 , C08L83/00 , C08L1/02 , C08K3/22
CPC分类号： C08J11/04 , C08J2323/02 , Y02P20/143 , Y02W30/70
摘要： The recycled thermosetting flour composites and method for preparing the same are disclosed. The silane coupling agent is used as a coincidental bridge between recycled thermosetting flour and plastic materials, to apparently promote the mechanical properties of composites by linking with each other. As a result, the recycled polyolefin and recycled thermosetting flour are applied through interfacial modification, coupling, modification, mixing and granulating process to generate a composite with better mechanical properties and recycle the resource.
摘要翻译：公开了回收的热固性粉末复合材料及其制备方法。硅烷偶联剂用作再循环热固性粉末和塑料材料之间的巧合桥梁，以显然通过彼此连接来促进复合材料的机械性能。结果，回收的聚烯烃和回收的热固性粉末通过界面改性，偶联，改性，混合和造粒工艺施加，以产生具有更好的机械性能和回收资源的复合材料。

10. 发明授权

US08453095B2 Systems and methods for creating frequency-dependent netlist 有权
标题翻译：用于创建频率相关网表的系统和方法
公开(公告)号：US08453095B2
公开(公告)日：2013-05-28
申请号：US13176823
申请日：2011-07-06
申请人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
发明人： Ke-Ying Su , Ching-Shun Yang , Jui-Feng Kuan , Hsiao-Shu Chao , Yi-Kan Cheng , Huang-Yu Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5077 , G06F17/5081
摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
摘要翻译：一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

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