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1. 发明授权

US2318867A Preservation of comestibles 失效
标题翻译：保存食物
公开(公告)号：US2318867A
公开(公告)日：1943-05-11
申请号：US29422539
申请日：1939-09-11
申请人： FELIX KIEFER
发明人： FELIX KIEFER
IPC分类号： A23C3/08 , A23L3/358 , C11B5/00
CPC分类号： A23L3/358 , A23C3/085 , C11B5/00 , C11B5/0078

2. 发明授权

US2347486A Preservation of comestibles 失效
标题翻译：保存食物
公开(公告)号：US2347486A
公开(公告)日：1944-04-25
申请号：US44418042
申请日：1942-05-23
申请人： FELIX KIEFER
发明人： FELIX KIEFER
IPC分类号： A23L3/3409
CPC分类号： A23L3/3409

3. 发明授权

US07613989B2 Decoder for executing a Viterbi algorithm 失效
标题翻译：用于执行维特比算法的解码器
公开(公告)号：US07613989B2
公开(公告)日：2009-11-03
申请号：US11199811
申请日：2005-08-09
申请人： Felix Kiefer , Miodrag Temerinac
发明人： Felix Kiefer , Miodrag Temerinac
IPC分类号： H03M13/03
CPC分类号： H03M13/4184 , H03M13/4107 , H03M13/6583
摘要： A Viterbi decoder includes a computing device, a memory and a bus. The computing device receives sets of data values and calculates distances for the received sets of data values, accumulates and compares the calculated distances according to a Viterbi algorithm, decides data values and generates control signals dependent on a plurality of decisions associated with a plurality of paths. The memory stores the decided data values and provides at least one output value. The bus connects the computing device and the memory and is configured to convey the control signals to the path memory. The computing device or the memory shifts data strings in the memory according to conditions of the Viterbi algorithm with the control signals associated with the plurality of paths.
摘要翻译：维特比解码器包括计算设备，存储器和总线。计算设备接收数据值集合并计算接收到的数据值集合的距离，根据维特比算法累积并比较计算出的距离，决定数据值，并根据与多个路径相关联的多个决定生成控制信号。存储器存储所决定的数据值并提供至少一个输出值。总线连接计算设备和存储器，并且被配置为将控制信号传送到路径存储器。计算设备或存储器根据具有与多个路径相关联的控制信号的维特比算法的条件来移动存储器中的数据串。

4. 发明申请

US20060209996A1 Decoder for executing a viterbi algorithm 失效
标题翻译：用于执行维特比算法的解码器
公开(公告)号：US20060209996A1
公开(公告)日：2006-09-21
申请号：US11199811
申请日：2005-08-09
申请人： Felix Kiefer , Miodrag Temerinac
发明人： Felix Kiefer , Miodrag Temerinac
IPC分类号： H03D1/00
CPC分类号： H03M13/4184 , H03M13/4107 , H03M13/6583
摘要： A Viterbi decoder includes a computing device that receives sets of data values and calculates distances from the received data values and accumulates and compares the distances according to a Viterbi algorithm and decides data values. Also included is a path memory for storing decided-upon data values. A bus connects the computing device and the path memory. The computing device generates control signals dependent on the decisions that are associated with paths. The bus conveys the control signals to the path memory. The computing device and/or the path memory shifts data strings with the control signals associated with the paths in the path memory according to conditions of the Viterbi algorithm. The path memory provides at least one output value. The computing device evaluates the requisite distances, for example all distances required for each set of received values (e.g., in one module), and accumulates and compares the associated distances according to the Viterbi algorithm, where, for example the relatively smallest distances may be selected and stored in a distance memory. The decoder may have a system clock frequency equal to the decoder cycle frequency or the data rate. As such, the number of accumulate-and-compare modules of the computing device are equal to the number of states, for example, paths. The bus width of the bus to the distance memory may be sized for reading and storing the distances for all paths at the same time, with the bus to the path memory carrying all the control signals at the same time.
摘要翻译：维特比解码器包括计算装置，其接收数据值集合并计算距接收数据值的距离，并且根据维特比算法累积并比较距离并且决定数据值。还包括用于存储确定的数据值的路径存储器。总线连接计算设备和路径存储器。计算设备根据与路径相关联的决策产生控制信号。总线将控制信号传送到路径存储器。计算设备和/或路径存储器根据维特比算法的条件，利用与路径存储器中的路径相关联的控制信号来移动数据串。路径存储器提供至少一个输出值。计算设备评估所需的距离，例如每组接收值所需的所有距离（例如，在一个模块中），并根据维特比算法累积和比较相关联的距离，其中例如相对较小的距离可以是选择并存储在距离存储器中。解码器可以具有等于解码器周期频率或数据速率的系统时钟频率。这样，计算设备的累加和比较模块的数量等于状态数量，例如路径。总线到距离存储器的总线宽度的大小可以被设置用于同时读取和存储所有路径的距离，同时总线与路径存储器同时承载所有的控制信号。

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