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1. 发明授权

US07034367B2 Semiconductor device having an STI structure and a dummy pattern with a rectangular shape 有权
标题翻译：具有STI结构的半导体器件和具有矩形形状的虚拟图案
公开(公告)号：US07034367B2
公开(公告)日：2006-04-25
申请号：US10781809
申请日：2004-02-20
申请人： Etsuyoshi Kobori
发明人： Etsuyoshi Kobori
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76229 , H01L21/31053
摘要： An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches; and c) removing a portion of the insulating film protruded from the trenches, thereby forming, in the trenches within the actual element region, a first embedded insulating film for isolation, and forming a second embedded insulating film in the trenches within the dummy pattern region. The dummy pattern region has dummy patterns in which no trenches are formed, and the widthwise size of each dummy pattern is four times or less of the depth of a portion of each trench provided in the substrate.
摘要翻译：一种用于制造半导体器件的发明方法包括以下步骤：a）通过使用掩模在衬底的实际元件区域和虚设图案区域中形成沟槽; b）在衬底上沉积绝缘体，从而形成至少填充沟槽的绝缘膜; 以及c）去除从所述沟槽突出的所述绝缘膜的一部分，从而在所述实际元件区域内的沟槽中形成用于隔离的第一嵌入绝缘膜，并且在所述虚设图案区域内的所述沟槽中形成第二嵌入绝缘膜。虚拟图案区域具有不形成沟槽的虚拟图案，并且每个虚设图案的宽度方向尺寸是设置在基板中的每个沟槽的一部分的深度的四倍或更小。

2. 发明申请

US20060145268A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060145268A1
公开(公告)日：2006-07-06
申请号：US11367556
申请日：2006-03-06
申请人： Etsuyoshi Kobori
发明人： Etsuyoshi Kobori
IPC分类号： H01L29/76
CPC分类号： H01L21/76229 , H01L21/31053
摘要： An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches; and c) removing a portion of the insulating film protruded from the trenches, thereby forming, in the trenches within the actual element region, a first embedded insulating film for isolation, and forming a second embedded insulating film in the trenches within the dummy pattern region. The dummy pattern region has dummy patterns in which no trenches are formed, and the widthwise size of each dummy pattern is four times or less of the depth of a portion of each trench provided in the substrate.
摘要翻译：一种用于制造半导体器件的发明方法包括以下步骤：a）通过使用掩模在衬底的实际元件区域和虚设图案区域中形成沟槽; b）在衬底上沉积绝缘体，从而形成至少填充沟槽的绝缘膜; 以及c）去除从所述沟槽突出的所述绝缘膜的一部分，从而在所述实际元件区域内的沟槽中形成用于隔离的第一嵌入绝缘膜，并且在所述虚设图案区域内的所述沟槽中形成第二嵌入绝缘膜。虚拟图案区域具有不形成沟槽的虚拟图案，并且每个虚设图案的宽度方向尺寸是设置在基板中的每个沟槽的一部分的深度的四倍或更小。

3. 发明授权

US06713847B1 Method of fabricating semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US06713847B1
公开(公告)日：2004-03-30
申请号：US09610148
申请日：2000-07-05
申请人： Etsuyoshi Kobori
发明人： Etsuyoshi Kobori
IPC分类号： H01L2940
CPC分类号： H01L21/76888 , H01L21/76801 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L21/76834
摘要： Wiring of the Dual-Damascene structure is formed without using the CMP method. As shown in FIG. 1A, oxygen ions are implanted from an upper surface under the condition that the oxygen ions reach a position a little deeper than the thickness t1 of the copper film 11 on the SiO2 layer 2. Due to the foregoing, as shown in FIG. 1B, the copper film 11 on the SiO2 layer 2 and the copper films on the upper portions of the first wiring section 18 and the second wiring section 19 are oxidized, and the oxidized layer 13 is formed. Since the dielectric constant of copper oxide is high, the first wiring section 18 and the second wiring section 19 are insulated from each other. Therefore, it is possible to obtain a highly reliable wiring structure easily.
摘要翻译：在不使用CMP方法的情况下形成双镶嵌结构的布线。如图1A所示，在氧离子到达比SiO2层2上的铜膜11的厚度t1稍深的位置的条件下，从上表面注入氧离子。如图1B所示，SiO 2层2上的铜膜11和第一配线部18以及第二配线部19的上部的铜膜被氧化，形成氧化层13。由于氧化铜的介电常数高，所以第一配线部18和第二配线部19彼此绝缘。因此，可以容易地获得高度可靠的布线结构。

4. 发明授权

US07022619B2 Method for fabricating electronic device 失效
公开(公告)号：US07022619B2
公开(公告)日：2006-04-04
申请号：US10395182
申请日：2003-03-25
申请人： Michinari Yamanaka , Hiroshi Yuasa , Tetsuo Satake , Etsuyoshi Kobori , Takeshi Yamashita , Susumu Matsumoto
发明人： Michinari Yamanaka , Hiroshi Yuasa , Tetsuo Satake , Etsuyoshi Kobori , Takeshi Yamashita , Susumu Matsumoto
IPC分类号： H01L21/302 , H01L21/461 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76808 , H01L21/76826
摘要： After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.

5. 发明授权

US6100190A Method of fabricating semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US6100190A
公开(公告)日：2000-08-08
申请号：US251425
申请日：1999-02-17
申请人： Etsuyoshi Kobori
发明人： Etsuyoshi Kobori
IPC分类号： H01L21/768 , H01L21/47
CPC分类号： H01L23/5223 , H01L21/76801 , H01L21/76834 , H01L21/7684 , H01L21/76888 , H01L2924/0002
摘要： Wiring of the Dual-Damascene structure is formed without using the CMP method.As shown in FIG. 1A, oxygen ions are implanted from an upper surface under the condition that the oxygen ions reach a position a little deeper than the thickness t1 of the copper film 11 on the SiO.sub.2 layer 2. Due to the foregoing, as shown in FIG. 1B, the copper film 11 on the SiO.sub.2 layer 2 and the copper films on the upper portions of the first wiring section 18 and the second wiring section 19 are oxidized, and the oxidized layer 13 is formed. Since the dielectric constant of copper oxide is high, the first wiring section 18 and the second wiring section 19 are insulated from each other. Therefore, it is possible to obtain a highly reliable wiring structure easily.
摘要翻译：在不使用CMP方法的情况下形成双镶嵌结构的布线。如图所示。如图1A所示，在氧离子到达比SiO2层2上的铜膜11的厚度t1稍深的位置的条件下，从上表面注入氧离子。如图1B所示，SiO 2层2上的铜膜11和第一配线部18以及第二配线部19的上部的铜膜被氧化，形成氧化层13。由于氧化铜的介电常数高，所以第一配线部18和第二配线部19彼此绝缘。因此，可以容易地获得高度可靠的布线结构。

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