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1. 发明授权

US06922047B2 Startup/yank circuit for self-biased phase-locked loops 失效
标题翻译：启动/匝电路用于自偏置锁相环
公开(公告)号：US06922047B2
公开(公告)日：2005-07-26
申请号：US10446838
申请日：2003-05-29
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： G01R23/12 , G01R31/02 , H03L7/00 , H03L7/06 , H03L7/089 , H03L7/12 , H03L7/18
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译：用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。在两种操作模式下控制锁相环的方法可以使用上述装置。

2. 发明申请

US20050044455A1 High-accuracy continuous duty-cycle correction circuit 有权
标题翻译：高精度连续工作周期校正电路
公开(公告)号：US20050044455A1
公开(公告)日：2005-02-24
申请号：US10645660
申请日：2003-08-22
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： G06F1/04 , G06K5/04 , G11B5/00 , G11B20/20 , H03K5/156
CPC分类号： G06F1/04 , H03K5/1565
摘要： A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than ±1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.
摘要翻译：控制电路在宽动态范围内精确地和快速连续的响应来校正时钟信号的占空比失真。在一个实施例中，占空比校正电路包括将占空比失真校正至优选小于±1％的自偏置环路。占空比校正电路还补偿电源电压的变化。不仅在测试期间，而且在由时钟信号驱动的主机系统的正常操作期间，这些校正可以连续进行。

3. 发明授权

US06329882B1 Third-order self-biased phase-locked loop for low jitter applications 有权
标题翻译：用于低抖动应用的三阶自偏置锁相环
公开(公告)号：US06329882B1
公开(公告)日：2001-12-11
申请号：US09468220
申请日：1999-12-20
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03L7093
CPC分类号： H03L7/0893 , H03L2207/06
摘要： A self-biased phase-locked loop circuit includes a phase detector, first and second charge pumps, first and second loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency in response to the control signal. The second loop filter capacitor considerably improves the output clock jitter.
摘要翻译：自偏置锁相环电路包括相位检测器，第一和第二电荷泵，第一和第二环路滤波器以及压控振荡器（VCO）。相位检测器被配置为测量两个输入信号之间的相位偏移，并且产生对应于相位偏移的脉冲。第一和第二电荷泵配置成提供对应于脉冲的电荷。第一和第二环路滤波器分别耦合到第一和第二电荷泵的输出端。滤波器操作以响应于电荷提供控制信号。 VCO被配置为响应于控制信号调整其输出频率。第二个环路滤波电容大大提高了输出时钟抖动。

4. 发明授权

US06233200B1 Method and apparatus for selectively disabling clock distribution 有权
标题翻译：选择性地禁用时钟分配的方法和装置
公开(公告)号：US06233200B1
公开(公告)日：2001-05-15
申请号：US09465220
申请日：1999-12-15
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： G11C800
CPC分类号： G06F1/10 , H03L7/095
摘要： A clock distribution network includes a phase-locked loop (PLL), clock buffers, an enabling circuit, and a distribution inhibit circuit. The PLL is configured to generate a clock signal and a lock detect signal. The clock buffers are adapted to receive the clock signal from the PLL. The buffers have outputs that can be connected to clock loads. The enabling circuit enables selected buffers to drive the clock loads. The distribution inhibit circuit selectively produces the enable signal to inhibit distribution of the clock signal responsive to the lock detect signal.
摘要翻译：时钟分配网络包括锁相环（PLL），时钟缓冲器，使能电路和分配禁止电路。 PLL被配置为产生时钟信号和锁定检测信号。时钟缓冲器适于从PLL接收时钟信号。缓冲器具有可连接到时钟负载的输出。启用电路使选定的缓冲区能够驱动时钟负载。分配禁止电路响应于锁定检测信号选择性地产生使能信号以禁止时钟信号的分配。

5. 发明授权

US6071003A Method and apparatus for locating critical speed paths in integrated circuits using a clock driver circuit with variable delay 失效
标题翻译：使用具有可变延迟的时钟驱动电路在集成电路中定位临界速度路径的方法和装置
公开(公告)号：US6071003A
公开(公告)日：2000-06-06
申请号：US774517
申请日：1996-12-30
申请人： Roni Ashuri , Ernest Knoll
发明人： Roni Ashuri , Ernest Knoll
IPC分类号： G01R31/30 , G06F17/50 , G06F17/00
CPC分类号： G01R31/3016 , G06F17/5031
摘要： A method and apparatus for locating a critical speed path in an integrated circuit. The operating frequency of the integrated circuit is increased until a logic error occurs in the integrated circuit. The propagation time of one clock signal within a circuit subblock of the integrated circuit is then increased until the logic error is eliminated. The propagation time of the clock signal is increased by enabling a delay circuit comprising a capacitor coupled to the clock signal. Another embodiment of the clock signal comprises a circuit that introduces contention on the clock signal line.
摘要翻译：一种用于在集成电路中定位临界速度路径的方法和装置。集成电路的工作频率增加，直到集成电路发生逻辑错误。然后增加集成电路的电路子块内的一个时钟信号的传播时间，直到消除逻辑误差。通过启用包括耦合到时钟信号的电容器的延迟电路来增加时钟信号的传播时间。时钟信号的另一实施例包括在时钟信号线上引入竞争的电路。

6. 发明申请

US20080157880A1 TEMPERATURE COMPENSATED LOOP FILTER 审中-公开
标题翻译：温度补偿环路滤波器
公开(公告)号：US20080157880A1
公开(公告)日：2008-07-03
申请号：US11618466
申请日：2006-12-29
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03L7/08 , G05D23/20
CPC分类号： H03L7/0891 , H03L7/093 , H03L2207/04
摘要： Disclosed herein are embodiments of a temperature compensating solution to reduce changes in PLL damping factor that would otherwise occur with changes in temperature.
摘要翻译：这里公开了温度补偿解决方案的实施例，以减少否则随着温度变化而发生的PLL阻尼因子的变化。

7. 发明申请

US20080136545A1 DELAY STAGE WITH CONTROLLABLY VARIABLE CAPACITIVE LOAD 有权
标题翻译：具有可变电容负载的延迟阶段
公开(公告)号：US20080136545A1
公开(公告)日：2008-06-12
申请号：US11609819
申请日：2006-12-12
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03B5/20 , H03L7/099
CPC分类号： H03B5/20 , H03K3/0315 , H03K5/133 , H03K2005/00045 , H03K2005/00071 , H03L7/0995
摘要： Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.
摘要翻译：这里公开的可控可变电容器负载的实施例可以与延迟级或其他元件一起使用，例如在压控振荡器中。

8. 发明授权

US07095289B2 Yank detection circuit for self-biased phase locked loops 有权
标题翻译：用于自偏置锁相环的Yank检测电路
公开(公告)号：US07095289B2
公开(公告)日：2006-08-22
申请号：US11122064
申请日：2005-05-05
申请人： Ernest Knoll , Eyal Fayneh
发明人： Ernest Knoll , Eyal Fayneh
IPC分类号： G01R23/12 , H03L7/00 , H03L7/099 , H03L7/06
CPC分类号： H03L7/10 , H03L7/0893 , H03L7/12 , H03L7/18
摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.
摘要翻译：用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。在两种操作模式下控制锁相环的方法可以使用上述装置。

9. 发明申请

US20060047986A1 Method and apparatus for controlling power management state transitions 有权
标题翻译：用于控制电源管理状态转换的方法和装置
公开(公告)号：US20060047986A1
公开(公告)日：2006-03-02
申请号：US10931565
申请日：2004-08-31
申请人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad Dendinger , Jorge Rodriguez , Ernest Knoll , David Poisner
发明人： Tsvika Kurts , Alon Naveh , Efraim Rotem , Brad Dendinger , Jorge Rodriguez , Ernest Knoll , David Poisner
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.
摘要翻译：诸如处理器的集成电路器件启动向第一电源管理状态的转变。然后，设备接收到退出第一电源管理状态的请求，并且响应于退出基准工作电压（例如最小工作电压）和当前电压的最高处的第一电源管理状态。一方面，可以使用模数转换器来确定当前的电压电平。此外，对于一个方面，第一功率管理状态可以是更深的睡眠（C4）状态，并且处理器可以响应于总线事件（例如总线监听）而快速退出到C2状态。

10. 发明授权

US06914490B2 Method for clock generator lock-time reduction during speedstep transition 失效
标题翻译：在速度转换过程中时钟发生器锁定时间减少的方法
公开(公告)号：US06914490B2
公开(公告)日：2005-07-05
申请号：US10446724
申请日：2003-05-29
申请人： Eyal Fayneh , Ernest Knoll
发明人： Eyal Fayneh , Ernest Knoll
IPC分类号： H03L7/089 , H03L7/093 , H03L7/107 , H03L7/00
CPC分类号： H03L7/107 , H03L7/0893 , H03L7/093 , H03L7/1072
摘要： A method for controlling a phase-locked loop includes receiving a frequency change signal and electrically isolating a VCO control node of the phase-locked loop from at least one charge pump of the loop. During this isolation period, the VCO control node voltage is held at a constant value equal to the voltage that existed before the frequency change signal was received. One or more parameters of the PLL are then altered in a manner that will ensure generation of a newly desired output frequency. These parameters include but are not limited to a feedback divider value and a reference frequency input into the PLL. The new output frequency may be above or below the pre-change signal frequency depending, for example, on a mode of operation of a host system. When the VCO control node is once again electrically connected to the charge pump, the PLL locks on to the desired output frequency. Through this method, frequency change is accomplished without performing a startup process and the time to perform a frequency acquisition process is significantly reduced.
摘要翻译：用于控制锁相环的方法包括接收频率变化信号并将锁相环的VCO控制节点与环路的至少一个电荷泵电隔离。在该隔离期间，VCO控制节点电压保持在等于接收到频率变化信号之前存在的电压的恒定值。 PLL的一个或多个参数然后以将确保新产生期望的输出频率的方式改变。这些参数包括但不限于输入到PLL中的反馈分频器值和参考频率。新的输出频率可以高于或低于预先改变的信号频率，这取决于例如主机系统的操作模式。当VCO控制节点再次电连接到电荷泵时，PLL锁定到期望的输出频率。通过这种方法，在不执行启动过程的情况下实现频率改变，并且显着地减少执行频率获取过程的时间。

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