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1. 发明授权

US08095857B2 Method and apparatus for joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations 有权
标题翻译：用于在多个符号持续时间内传输的多维码的联合均衡和解码的方法和装置
公开(公告)号：US08095857B2
公开(公告)日：2012-01-10
申请号：US10022665
申请日：2001-12-18
申请人： Kameran Azadet , Erich Franz Haratsch
发明人： Kameran Azadet , Erich Franz Haratsch
IPC分类号： H03M13/03
CPC分类号： H04L25/03006 , H03M13/256 , H03M13/39 , H03M13/3961 , H03M13/4107 , H03M13/6331 , H04L25/03305
摘要： A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. In addition, the disclosed RSSE decoder compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.
摘要翻译：公开了一种用于执行在多个符号持续时间上发送的多维码的联合均衡和解码的方法和装置。公开了一种RSSE方案，其消除由同一多维码符号内的其他符号分量引起的内部符号干扰。所披露的用于多维码的RSSE技术适用于网格码数量超过信道数量的地方。所公开的RSSE解码器计算由先前解码的多维码符号引起的符号间干扰。此外，分支度量单元补偿由相同的多维码符号内的其他符号分量引起的内部符号干扰。另外，所公开的RSSE解码器补偿由相同的多维码符号内的其他符号分量引起的内部符号干扰。

2. 发明授权

US07937649B2 Reliability unit for determining a reliability value for at least one bit decision 有权
标题翻译：用于确定至少一个位决定的可靠性值的可靠性单元
公开(公告)号：US07937649B2
公开(公告)日：2011-05-03
申请号：US12547888
申请日：2009-08-26
申请人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
发明人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
IPC分类号： H03M13/03
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.
摘要翻译：提供了用于确定至少一个位决定的可靠性值的可靠性单元。所公开的可靠性单元包括一个或多个功能元件，其中每个功能元件包括至少四个功能单元和至少两个寄存器，其中每个功能单元包括比较器和多路复用器，并且其中比较器的输出和等效位控制多路复用器。通常，可靠性单元确定与通过多步网格的最大似然路径相关联的位决定的可靠性值。

3. 发明授权

US07656959B2 Pipelined decision-feedback unit in a reduced-state viterbi detector with local feedback 有权
标题翻译：在具有本地反馈的简化状态维特比检测器中的流水线判决反馈单元
公开(公告)号：US07656959B2
公开(公告)日：2010-02-02
申请号：US10962188
申请日：2004-10-08
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H04L5/12 , H04L23/02
CPC分类号： H04L25/03235 , H03M13/03 , H04L25/03057 , H04L25/4917
摘要： A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.
摘要翻译：公开了一种流水线判决反馈单元（DFU），用于具有本地反馈的简化状态维特比检测器。所公开的流水线判决反馈单元通过基于部分符号间干扰的估计的流水线计算提高了通过简化状态维特比检测器可以实现的最大数据速率。因此公开了流水线判决反馈单元，其计算多个基于部分符号间干扰的估计，其中至少一个部分符号间干扰估计基于所选择的部分符号间干扰估计; 并且将所选择的部分符号间干扰估计从用于路径扩展的部分符号间干扰估计中选择为状态。

4. 发明申请

US20090292974A1 METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING 有权
公开(公告)号：US20090292974A1
公开(公告)日：2009-11-26
申请号：US12533432
申请日：2009-07-31
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/455 , H03M13/154
摘要： Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.

5. 发明授权

US08879182B2 Storage media inter-track interference cancellation 有权
标题翻译：存储介质轨道间干扰消除
公开(公告)号：US08879182B2
公开(公告)日：2014-11-04
申请号：US13591937
申请日：2012-08-22
申请人： Erich Franz Haratsch , George Mathew , Ming Jin , Jongseung Park , Timothy W. Swatosh , Timothy B. Lund , Carl E. Forhan
发明人： Erich Franz Haratsch , George Mathew , Ming Jin , Jongseung Park , Timothy W. Swatosh , Timothy B. Lund , Carl E. Forhan
IPC分类号： G11B5/09 , G11B20/10 , G11B19/04 , G11B5/012 , G11B20/14 , G11B20/12 , G11B20/18
CPC分类号： G11B5/09 , G11B5/012 , G11B19/045 , G11B20/10046 , G11B20/10212 , G11B20/10462 , G11B20/1217 , G11B20/1423 , G11B2020/10759 , G11B2020/1232 , G11B2020/1298 , G11B2020/183 , G11B2020/185 , G11B2020/1856 , G11B2220/2516
摘要： Described embodiments provide a method of cancelling inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A road channel reads sectors in a desired track of the storage medium. A decoder of the read channel decodes the read sectors, and if the read sectors are incorrectly recovered from the storage medium, selected sectors of a first adjacent track and a second adjacent track are read. An ITI canceller of the read channel estimates ITI in the read sectors of the desired track corresponding to the selected sectors of each adjacent track and subtracts the estimated ITI of each adjacent track from the data for the sectors of the desired track, providing updated sector data. The ITI cancelled data is replayed to the decoder, which decodes the ITI cancelled data and provides the decoded ITI cancelled data as output of the read channel.
摘要翻译：所描述的实施例提供了从存储介质的期望轨迹读取的一个或多个扇区消除轨道间干扰（ITI）的方法。道路通道读取存储介质的期望轨道中的扇区。读通道的解码器解码读扇区，并且如果从存储介质中错误地恢复读扇区，则读取第一相邻轨道和第二相邻轨道的选定扇区。读通道的ITI消除器估计对应于每个相邻磁道的所选扇区的期望磁道的读扇区中的ITI，并从期望磁道的扇区的数据中减去每个相邻磁道的估计ITI，从而提供更新的扇区数据。 ITI取消的数据被重播到解码器，解码器解码ITI取消的数据，并将解码的ITI取消数据作为读通道的输出。

6. 发明授权

US07913154B2 Method and apparatus for pipelined joint equalization and decoding for gigabit communications 有权
标题翻译：用于千兆通信的流水线联合均衡和解码的方法和装置
公开(公告)号：US07913154B2
公开(公告)日：2011-03-22
申请号：US12039474
申请日：2008-02-28
申请人： Kameran Azadet , Erich Franz Haratsch
发明人： Kameran Azadet , Erich Franz Haratsch
IPC分类号： H03M13/03
CPC分类号： H03M13/6331 , H03M13/03 , H04L25/03057 , H04L25/03235 , H04L25/4917
摘要： A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.
摘要翻译：公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行）的增加的吞吐量相对于先行深度仅具有线性增加的硬件复杂度。本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

7. 发明申请

US20100050060A1 Path Comparison Unit For Determining Paths In A Trellis That Compete With A Survivor Path 有权
标题翻译：用于确定与幸存者路径竞争的网格中的路径的路径比较单元
公开(公告)号：US20100050060A1
公开(公告)日：2010-02-25
申请号：US12547862
申请日：2009-08-26
申请人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
发明人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
IPC分类号： H03M13/25 , G06F11/08
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.
摘要翻译：公开了一种用于确定与幸存路径竞争的网格中的路径的路径比较单元。所公开的路径比较单元包括第一类型功能单元，包括多路复用器和寄存器，用于存储与幸存路径相关联的一个或多个幸存者位; 和至少两个第二类型功能单元，其中每个第二类型功能单元包括多路复用器和逻辑电路，用于计算指示相应路径的位是否相等的至少一个等同位。通常，相应的路径是失败路径和失败路径中的一个或多个。

8. 发明授权

US07653154B2 Method and apparatus for precomputation and pipelined selection of intersymbol interference estimates in a reduced-state Viterbi detector 有权
标题翻译：用于预先计算的方法和装置，以及在还原状态维特比检测器中流水线选择符号间干扰估计
公开(公告)号：US07653154B2
公开(公告)日：2010-01-26
申请号：US10853088
申请日：2004-05-25
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H04L27/06
CPC分类号： H04L25/03235 , G11B20/10009 , H03M13/256 , H03M13/4107 , H03M13/4192 , H03M13/6502 , H04L25/03197
摘要： A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced-state Viterbi detectors is improved by precomputing a number of candidate intersymbol interference estimates and performing pipelined selection of an appropriate intersymbol interference estimate. A reduced-state Viterbi detector is thus disclosed that precomputes intersymbol interference estimates for speculative sequences of one or more channel symbols; selects one of said precomputed intersymbol interference estimates based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state. In an alternative implementation, intersymbol interference estimate-free signal estimates are selected among precomputed ones.
摘要翻译：公开了一种用于利用本地反馈来提高降维态维特比检测器的最大数据速率的方法和装置。通过预先计算多个候选符号间干扰估计并执行适当的符号间干扰估计的流水线选择，可以改善所公开的降维态维特比检测器可以实现的最大数据速率。因此，公开了一种缩减状态维特比检测器，其预先计算一个或多个信道符号的推测序列的符号间符号干扰估计; 基于使用至少两个流水线寄存器的至少一个对应状态的至少一个判决来选择所述预计算码间干扰估计之一; 并为给定状态选择具有最佳路径度量的路径。在替代实现中，在预先计算的信号估计中选择符号间干扰估计。

9. 发明授权

US07607072B2 Method and apparatus for-soft-output viterbi detection using a multiple-step trellis 有权
标题翻译：使用多步网格进行软输出维特比检测的方法和装置
公开(公告)号：US07607072B2
公开(公告)日：2009-10-20
申请号：US11045585
申请日：2005-01-28
申请人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
发明人： Jonathan James Ashley , Kelly Knudson Fitzpatrick , Erich Franz Haratsch
IPC分类号： H03M13/00
CPC分类号： H03M13/4192 , H03M13/395 , H03M13/4153
摘要： Methods and apparatus are provided for performing Soft-Output Viterbi Algorithm (SOVA) detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).
摘要翻译：提供了用于以比常规设计可实现的更高数据速率执行软输出维特比算法（SOVA）检测的方法和装置。接收到的信号通过以下步骤来处理：（i）确定至少三个选择信号，其将通过多步网格的多个路径定义到给定状态，其中多条路径中的第一条路径是用于每个单步路段的获胜路径，多步骤格雷周期的网格周期，第二路径是第一单步网格周期的获胜路径，并且是多步骤网格周期的第二单步网格周期的丢失路径，并且第三条路径是第一个单步网格周期的失败之路，是多阶段格雷周期的第二个单步阶段的获胜路径; 和（ii）确定至少一个可靠性值（诸如与通过多步网格的最大似然路径相关联的比特决定的可靠性值或每个多步网格周期的多个可靠性值）。

10. 发明申请

US20090129519A1 METHOD AND APPARATUS FOR JOINT EQUALIZATION AND DECODING OF MULTILEVEL CODES 有权
标题翻译：用于联合平均化和解码多种编码的方法和装置
公开(公告)号：US20090129519A1
公开(公告)日：2009-05-21
申请号：US12359778
申请日：2009-01-26
申请人： Kameran Azadet , Erich Franz Haratsch
发明人： Kameran Azadet , Erich Franz Haratsch
IPC分类号： H04L27/06
CPC分类号： H04L25/4923 , H04L25/03229 , H04L2025/03363
摘要： A method and apparatus are disclosed for joint equalization and decoding of multilevel codes, such as the MLT-3 code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm.
摘要翻译：公开了一种用于联合均衡和解码多级代码的方法和装置，例如在色散信道上传输的MLT-3码。 MLT-3代码被视为由有限状态机使用在各种状态之间具有状态依赖性的网格生成的代码。超级网格将MLT-3网格与网络格式的通道连接起来。接收信号的联合均衡和解码可以使用超级格子进行。公开了一种序列检测器，其使用超级格或相应的缩减状态网格来对接收到的信号进行联合均衡和解码，以解码MLT-3编码的数据位。可以使用应用最优维特比算法或缩减复杂度序列估计方法（例如缩减状态序列估计（RSSE）算法）的最大似然序列估计来体现序列检测器。

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