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1. 发明授权

US06769055B1 Two-part memory address generator 失效
标题翻译：两部分内存地址生成器
公开(公告)号：US06769055B1
公开(公告)日：2004-07-27
申请号：US09263948
申请日：1999-03-08
申请人： Eric Tsin-Ho Leung , Ching Yu
发明人： Eric Tsin-Ho Leung , Ching Yu
IPC分类号： G06F1200
CPC分类号： H04L47/24 , H04L49/15 , H04L49/3036 , H04L49/351 , H04L49/90
摘要： A memory address generator for a multiport data communication system storing received data packets in a memory having a plurality of storage areas. The data communication system has a plurality of receive ports receiving the data packets and a queue of addresses of a plurality of storage areas in the memory available for storing the received data packets. The address generator generates memory addresses to store the received data packets in the plurality of storage areas of the memory and includes first and second registers. The first register receives an address from the queue of addresses and provides a first part of the memory address, and the second register counts write cycles to the memory and provides the count result as a second part of the memory address.
摘要翻译：一种用于多端口数据通信系统的存储器地址发生器，其将接收到的数据分组存储在具有多个存储区域的存储器中。数据通信系统具有接收数据分组的多个接收端口和可用于存储接收到的数据分组的存储器中的多个存储区域的地址队列。地址生成器生成存储器地址以将接收到的数据分组存储在存储器的多个存储区域中，并且包括第一和第二寄存器。第一个寄存器从地址队列接收地址，并提供存储器地址的第一部分，第二个寄存器对存储器计数写入周期，并将计数结果作为存储器地址的第二部分提供。

2. 发明授权

US06574231B1 Method and apparatus for queuing data frames in a network switch port 有权
标题翻译：在网络交换机端口排队数据帧的方法和装置
公开(公告)号：US06574231B1
公开(公告)日：2003-06-03
申请号：US09316181
申请日：1999-05-21
申请人： Eric Tsin-Ho Leung
发明人： Eric Tsin-Ho Leung
IPC分类号： H04L1228
CPC分类号： H04L49/351 , H04L49/205 , H04L49/3027 , H04L49/352
摘要： A method and apparatus in a network switch port for providing queuing of data frames as they are transferred from a switch port to an external memory. Multiple buffers within the external memory used to store a single data frame are linked together by writing a next buffer location in each buffer header. Storing linking information within each buffer eliminates the need for a separate memory for storing all the buffer locations used to store a data frame, thereby reducing the complexity and cost of the network switch port.
摘要翻译：一种网络交换机端口中的方法和装置，用于在从交换机端口传输到外部存储器时提供数据帧的排队。用于存储单个数据帧的外部存储器中的多个缓冲区通过在每个缓冲区头中写入下一个缓冲区位置而链接在一起。在每个缓冲区内存储链接信息不需要单独的存储器来存储用于存储数据帧的所有缓冲区，从而降低了网络交换机端口的复杂性和成本。

3. 发明授权

US06393028B1 Method and apparatus for providing EOF for frame modification 有权
标题翻译：用于提供框架修改的EOF的方法和装置
公开(公告)号：US06393028B1
公开(公告)日：2002-05-21
申请号：US09257512
申请日：1999-02-25
申请人： Eric Tsin-Ho Leung
发明人： Eric Tsin-Ho Leung
IPC分类号： H04L1254
CPC分类号： H04L49/354 , H04L49/20 , H04L49/253 , H04L49/30 , H04L49/3009 , H04L49/3054 , H04L49/351 , H04L49/352 , H04L49/45
摘要： A multiport data communication system for switching data packets between ports comprising a plurality of receive ports for receiving data packets, a memory storing the received data packets, and a plurality of transmit ports each having a transmit queue. Logic circuitry for each transmit port controls reading of a data packet from memory, provides a control signal indicating an end of reading the data packet from the memory, decides whether a length of the read data packet is to increase, decrease, or remain the same, controls writing the read data packet to a corresponding transmit queue in accordance with the decision, and provides a signal indicating an end of writing the data packet to the transmit queue. To generate the end of reading of the data packet from memory, the logic circuitry determines a number of read operations necessary to read the data packet, corresponding to read address data from the memory, counts each read operation, and provides the signal indicating an end of reading the data packet from the memory when the counted read operations are equal to the number of determined read operations. To generate the end of writing the data packet to the transmit queue, the logic circuitry determines a number of write operations necessary to write the data packet which is modified/unmodified in accordance with decision as to whether a length of the read data packet is to increase, decrease, or remain the same, counts each write operation, and provides the signal indicating an end of writing the data packet to the transmit queue when the counted write operations are equal to the number of determined write operations.
摘要翻译：一种用于在包括用于接收数据分组的多个接收端口的端口之间切换数据分组的多端口数据通信系统，存储接收到的数据分组的存储器以及各自具有发送队列的多个发送端口。每个发送端口的逻辑电路控制从存储器读取数据分组，提供指示从存储器读取数据分组的结束的控制信号，决定读取的数据分组的长度是增加还是保持不变控制根据该决定将读取的数据包写入对应的发送队列，并且向发送队列提供指示将数据包写入结束的信号。为了产生从存储器读取数据分组的结束，逻辑电路确定读取数据分组所需的多个读取操作，对应于来自存储器的读取地址数据，对每个读取操作进行计数，并提供指示结束的信号当计数的读取操作等于所确定的读取操作的数量时，从存储器读取数据分组。为了产生将数据分组写入发送队列的结束，逻辑电路根据关于读取的数据分组的长度是否被修改/修改的决定来确定写入被修改/未修改的数据分组所需的多个写入操作增加，减少或保持相同，计数每个写入操作，并且当计数的写入操作等于确定的写入操作的数量时，提供指示将数据分组写入发送队列的结束的信号。

4. 发明授权

US06515990B1 Dequeuing logic architecture and operation in a multiport communication switch 有权
标题翻译：在多端口通信交换机中排队逻辑架构和操作
公开(公告)号：US06515990B1
公开(公告)日：2003-02-04
申请号：US09281900
申请日：1999-03-31
申请人： Eric Tsin-Ho Leung
发明人： Eric Tsin-Ho Leung
IPC分类号： H04L1228
CPC分类号： H04L49/90 , H04L47/50
摘要： A multiport data communication system for switching data packets between ports having a memory storing received data packets and a plurality of ports for transmitting and receiving data packets. Each transmit port has a transmit queue storing data packets to be transmitted from the respective port. The system includes a plurality of output queues, each corresponding to a respective port and storing frame pointers that point to where the data packets are stored in the memory. A plurality of dequeuing logic circuitry is provided corresponding to the plurality of ports. Each dequeuing logic circuitry reads respective frame pointers from the plurality of queues, reads the respective data packets corresponding to the respective frame pointers from the memory, and writes each read data packet to the corresponding transmit queue. The operations of each dequeuing logic circuitry are carried out in a pipelined manner in order to fully utilize the bandwidth of the external memory and speed up the dequeuing process. Consequently, there is no idle time between completing of reading of one data packet from the memory and beginning of reading of a subsequent data packet from the memory or between completing writing of one data packet to the corresponding transmit queue and 4.
摘要翻译：一种用于在具有存储接收数据分组的存储器和用于发送和接收数据分组的多个端口的端口之间切换数据分组的多端口数据通信系统。每个发送端口具有发送队列，其存储要从相应端口发送的数据分组。该系统包括多个输出队列，每个输出队列对应于相应的端口，并且存储指向数据分组被存储在存储器中的位置的指针。对应于多个端口提供多个出列逻辑电路。每个出队逻辑电路读取来自多个队列的相应帧指针，从存储器中读取与各个帧指针相对应的相应数据分组，并将每个读取的数据分组写入相应的发送队列。每个出列逻辑电路的操作以流水线方式执行，以便充分利用外部存储器的带宽并加速出队过程。因此，在从存储器读取一个数据分组和从存储器读取后续数据分组的完成之间或在完成一个数据分组到相应的发送队列的写入之间没有空闲时间4。

5. 发明授权

US06501734B1 Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port 有权
标题翻译：网络交换机中的装置和方法，用于在千兆端口和扩展端口之间动态分配存储器接口槽
公开(公告)号：US06501734B1
公开(公告)日：2002-12-31
申请号：US09317150
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04J116
CPC分类号： H04L49/103 , H04L49/254 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/90 , H04L49/901
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.
摘要翻译：具有根据以太网（IEEE 802.3）协议的具有各个网络节点的数据分组全双工通信的交换机端口的网络交换机动态地在高数据速率端口之间分配外部存储器带宽时隙。外部存储器接口确定高数据速率端口是否对带宽槽进行请求，如果发出请求则确定该请求。时隙是从所选择的组中获取的，该组是总时隙数的子集。如果没有对插槽进行请求，则外部存储器接口将插槽分配给另一个高数据速率端口。网络交换机中的较低数据速率端口从这些时隙中分配固定时隙，而不是在所选择的时隙组内。高数据速率端口之间的带宽时隙的动态分配使得能够有效地利用有限的存储器带宽资源。

6. 发明授权

US06466580B1 Method and apparatus for processing high and low priority frame data transmitted in a data communication system 失效
标题翻译：用于处理在数据通信系统中发送的高优先级和低优先级帧数据的方法和装置
公开(公告)号：US06466580B1
公开(公告)日：2002-10-15
申请号：US09255707
申请日：1999-02-23
申请人： Eric Tsin-Ho Leung
发明人： Eric Tsin-Ho Leung
IPC分类号： H04L1228
CPC分类号： H04L49/351 , H04L49/205 , H04L49/3027 , H04L49/352
摘要： A multiport data communication system for switching data packets between ports includes a plurality of receive ports for receiving data packets, a plurality of transmit ports for transmitting data packets, circuitry deciding whether each received data packet is one of high priority and low priority, and a memory for storing each received data packet. A memory location designator is provided for each data packet indicating where the corresponding data packet is stored in the memory and a plurality of queuing devices corresponding to the plurality of transmit ports queue the memory location designators. Each queuing device has a high priority queue queuing memory location designators corresponding to data packets of high priority to be retrieved from the memory an transmitted by the respective transmit port and a low priority queue queuing memory location designators corresponding to data packets of low priority to be retrieved from the memory and transmitted by the respective transmit port. Transferring circuitry transfers the data packets from the memory to a transmit queue corresponding to each respective transmit port and includes logic circuitry corresponding to each transmit queue. The logic circuitry determines whether the low priority queue of a respective queuing device has a memory location designator for a data packet to be retrieved from the memory and sent to the corresponding transmit queue only when the high priority queue of the respective queuing device is empty of memory location designators.
摘要翻译：用于在端口之间切换数据分组的多端口数据通信系统包括用于接收数据分组的多个接收端口，用于发送数据分组的多个发送端口，决定每个接收的数据分组是高优先级还是低优先级的电路，用于存储每个接收的数据分组的存储器。为每个数据分组提供存储器位置指示符，指示对应的数据分组存储在存储器中的位置，以及对应于多个发送端口的多个排队设备排队存储器位置指示符。每个排队装置具有高优先级队列排队存储器位置指示符，对应于要从存储器检索的高优先级的数据分组，由相应的发送端口发送;以及低优先级队列排队与低优先级的数据分组对应的存储器位置指示符，从存储器检索并由相应的发送端口发送。传输电路将数据分组从存储器传送到对应于每个相应发送端口的发送队列，并且包括对应于每个发送队列的逻辑电路。逻辑电路确定相应排队设备的低优先级队列是否具有用于要从存储器检索的数据分组的存储器位置指示符，并且仅当相应排队设备的高优先级队列空时才发送到相应的发送队列内存位置指示符。

7. 发明授权

US06597693B1 Common scalable queuing and dequeuing architecture and method relative to network switch data rate 有权
标题翻译：相对于网络交换机数据速率的通用可扩展排队和出队架构和方法
公开(公告)号：US06597693B1
公开(公告)日：2003-07-22
申请号：US09316182
申请日：1999-05-21
申请人： Eric Tsin-Ho Leung
发明人： Eric Tsin-Ho Leung
IPC分类号： H04L1100
CPC分类号： H04L49/351 , H04L49/3027 , H04L49/90
摘要： A network switch arrangement and method for providing a common architecture for queuing and dequeuing of data frames as they are transferred from a switch port to an external memory and similarly retrieved from the external memory to the switch port, irrespective of the particular data rate of the port. Logic controlling the actual data path is partitioned from logic responding to port data rate information by providing a “handshaking” communication arrangement between the two logics independent of the data rate. Hence, scalability of the data path over a wide range of data rates may be achieved while maintaining a single, common logic architecture.
摘要翻译：一种网络交换机布置和方法，用于提供用于在数据帧从交换机端口传送到外部存储器时排队和排队数据帧的公共架构，并且类似地从外部存储器检索到交换机端口，而不管数据帧的特定数据速率如何港口。通过在独立于数据速率的两个逻辑之间提供“握手”通信布置，将控制实际数据路径的逻辑与响应于端口数据速率信息的逻辑进行分区。因此，可以在保持单个公共逻辑架构的同时实现数据路径在宽范围的数据速率上的可扩展性。

8. 发明授权

US06442137B1 Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port 失效
标题翻译：用于交换千兆端口和扩展端口之间的存储器访问槽的网络交换机中的装置和方法
公开(公告)号：US06442137B1
公开(公告)日：2002-08-27
申请号：US09317143
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04L522
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/90 , H04L49/9031 , H04L49/9078
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.
摘要翻译：网络交换机具有用于根据以太网（IEEE 802.3）协议的具有各网络节点的数据分组全双工通信的交换机端口，该协议基于网络流量的比较量在高数据速率端口之间分配规定数量的外部存储器带宽时隙各个端口。外部存储器接口中的调度器根据规定的顺序，初始地将存储器访问时隙分配给相应的高数据速率端口。如果调度器随后检测到具有较少时隙的端口上的网络数据流量高于具有更多时隙的端口上的流量，则这些时隙在高数据速率端口之间交换。此外，高数据速率端口之一中的时钟多路复用器根据分配给该端口的时隙数来调整端口的数据速率。在高数据速率端口之间交换带宽时隙以及端口时钟速率的调整使得能够有效地使用有限的存储器带宽资源。

9. 发明授权

US6091707A Methods and apparatus for preventing under-flow conditions in a multiple-port switching device 失效
标题翻译：用于防止多端口开关装置中的欠流条件的方法和装置
公开(公告)号：US6091707A
公开(公告)日：2000-07-18
申请号：US993886
申请日：1997-12-18
申请人： Chandan Egbert , Bahadir Erimli , Eric Tsin-Ho Leung , Thomas J. Runaldue
发明人： Chandan Egbert , Bahadir Erimli , Eric Tsin-Ho Leung , Thomas J. Runaldue
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/54
CPC分类号： H04L49/351 , H04L49/103 , H04L49/105 , H04L49/30 , H04Q11/0478 , H04L2012/5649 , H04L2012/5651 , H04L49/20 , H04L49/3009 , H04L49/3027 , H04L49/3054 , H04L49/354
摘要： An interface for use in a data forwarding device is connected between the receive ports and transmit ports of a device. The interface ensures that data being forwarded from a receive port to a transmit port has actually been received. The interface includes a queuing circuit and a de-queuing circuit. The queuing circuit receives data from the receive port, identifies the receive port, counts the data received, and buffers the data. The de-queuing circuit retrieves the buffered data at a scheduled time based on the receive port's mode, and forwards the data to a transmit port provided that the amount of data received by the queuing circuit is at least as great as the amount of data already forwarded by the de-queuing circuit plus a threshold safe level amount of data.
摘要翻译：用于数据转发设备的接口连接在设备的接收端口和发送端口之间。该接口确保从接收端口转发到发送端口的数据已被实际接收。接口包括排队电路和排队电路。排队电路从接收端口接收数据，识别接收端口，对接收到的数据进行计数，并缓冲数据。排队电路基于接收端口的模式在预定的时间检索缓冲的数据，并且将数据转发到发送端口，只要排队电路接收的数据量至少与数据量一样大由排队电路转发加上阈值安全级别的数据量。

10. 发明授权

US07031305B1 Apparatus and method for programmable memory access slot assignment 有权
标题翻译：可编程存储器存取槽分配的装置和方法
公开(公告)号：US07031305B1
公开(公告)日：2006-04-18
申请号：US09317156
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04L12/28
CPC分类号： H04L49/351 , H04L49/205 , H04L49/3027 , H04L49/354
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.
摘要翻译：根据以太网（IEEE 802.3）协议，具有根据可编程信息灵活地分配存储器访问时隙以访问外部存储器的数据分组与各网络节点全双工通信的交换机端口的网络交换机。外部存储器接口中的调度器根据从外部可编程数据存储设备写入指配表存储器的编程序列，将存储器访问时隙分配给相应的网络交换机端口。

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