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1. 发明授权

US08898396B2 Software pipelining on a network on chip 有权
标题翻译：软件流水线在片上网络上
公开(公告)号：US08898396B2
公开(公告)日：2014-11-25
申请号：US13453380
申请日：2012-04-23
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/879 , H04L12/933 , H04L12/861 , H04L12/935 , H04L12/947
CPC分类号： H04L49/15 , H04L49/109 , H04L49/252 , H04L49/3036 , H04L49/90 , H04L49/901
摘要： Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.
摘要翻译：在芯片上的软件管道（“NOC”）中的内存共享，NOC包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，包括将计算机软件应用程序分段成软件流水线的阶段，所述软件流水线包括一个或多个执行路径; 在至少两个阶段中分配要共享的存储器，包括创建智能指针，所述智能指针包括用于确定何时可以释放所述共享存储器的数据元素; 根据用于确定何时可以释放共享存储器的数据元素确定可以释放共享存储器; 并释放共享内存。

2. 发明授权

US08719455B2 DMA-based acceleration of command push buffer between host and target devices 失效
标题翻译：主机和目标设备之间基于DMA的加速命令推送缓冲区
公开(公告)号：US08719455B2
公开(公告)日：2014-05-06
申请号：US12824674
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： Direct Memory Access (DMA) is used in connection with passing commands between a host device and a target device coupled via a push buffer. Commands passed to a push buffer by a host device may be accumulated by the host device prior to forwarding the commands to the push buffer, such that DMA may be used to collectively pass a block of commands to the push buffer. In addition, a host device may utilize DMA to pass command parameters for commands to a command buffer that is accessible by the target device but is separate from the push buffer, with the commands that are passed to the push buffer including pointers to the associated command parameters in the command buffer.
摘要翻译：直接存储器访问（DMA）用于在通过推送缓冲器耦合的主机设备和目标设备之间传递命令。由宿主设备传递到推送缓冲器的命令可以在将命令转发到推送缓冲器之前被主机设备累积，使得可以使用DMA来共同地将一组命令传递给推送缓冲器。此外，主机设备可以利用DMA将用于命令的命令参数传递给目标设备可访问但与推送缓冲区分离的命令缓冲区，其中传递到推送缓冲器的命令包括指向相关命令的指针命令缓冲区中的参数。

3. 发明授权

US08692825B2 Parallelized streaming accelerated data structure generation 失效
标题翻译：并行流加速数据结构生成
公开(公告)号：US08692825B2
公开(公告)日：2014-04-08
申请号：US12822427
申请日：2010-06-24
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/06 , G06T2200/28 , G06T2210/52
摘要： A method includes receiving at a master processing element primitive data that includes properties of a primitive. The method includes partially traversing a spatial data structure that represents a three-dimensional image to identify an internal node of the spatial data structure. The internal node represents a portion of the three-dimensional image. The method also includes selecting a slave processing element from a plurality of slave processing elements. The selected processing element is associated with the internal node. The method further includes sending the primitive data to the selected slave processing element to traverse a portion of the spatial data structure to identify a leaf node of the spatial data structure.
摘要翻译：一种方法包括在主处理元件处接收包括原语的属性的原始数据。该方法包括部分地遍历表示三维图像以识别空间数据结构的内部节点的空间数据结构。内部节点表示三维图像的一部分。该方法还包括从多个从属处理元件中选择从属处理元件。所选择的处理元件与内部节点相关联。该方法还包括将原始数据发送到所选择的从属处理元件以遍历空间数据结构的一部分以识别空间数据结构的叶节点。

4. 发明授权

US08514232B2 Propagating shared state changes to multiple threads within a multithreaded processing environment 有权
标题翻译：将共享状态更改传播到多线程处理环境中的多个线程
公开(公告)号：US08514232B2
公开(公告)日：2013-08-20
申请号：US12824778
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/80
CPC分类号： G06F12/0813 , G06T15/005
摘要： A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications network and without attempting to access any copy of the shared state data in a shared memory to which the parallel threads of execution are also coupled.
摘要翻译：电路布置和方法通过使用片上通信网络在多线程环境中传播或将变化传播或传输到多个并行硬件执行线程而不尝试访问任何副本，从而使状态对高度多线程环境中的共享状态数据进行改变并行线程执行的共享存储器中的共享状态数据也被耦合。

5. 发明授权

US08494833B2 Emulating a computer run time environment 有权
标题翻译：模拟电脑运行时环境
公开(公告)号：US08494833B2
公开(公告)日：2013-07-23
申请号：US12118059
申请日：2008-05-09
申请人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F9/45533
摘要： Emulating a computer run time environment including: storing translated code in blocks of a translated code cache, each block of the translated code cache designated for storage of translated code for a separate one of the target executable processes, including identifying each block in dependence upon an identifier of the process for which the block is designated as storage; executing by the emulation environment a particular one of the target executable processes, using for target code translation the translated code in the block of the translated code cache designated as storage for the particular process; and upon encountering a context switch by the target operating system to execution of a new target executable process, changing from the block designated for the particular process to using for target code translation the translated code in the block of the translated code cache designated as storage for the new target executable process.
摘要翻译：模拟计算机运行时间环境，包括：将转换后的代码存储在翻译的代码高速缓存的块中，转换的代码缓存的每个块被指定用于存储针对目标可执行进程的单独的一个的转换的代码，包括依赖于将块指定为存储的进程的标识符; 由仿真环境执行目标可执行过程中的特定一个，使用目标代码将被转换的代码缓存的块中的转换后的代码转换为特定进程的存储; 并且当遇到由目标操作系统执行新的目标可执行过程的上下文切换时，从为特定进程指定的块改变为使用目标代码转换所转换的代码缓存的块中被转换的代码缓存指定为存储新的目标可执行过程。

6. 发明授权

US08473667B2 Network on chip that maintains cache coherency with invalidation messages 有权
标题翻译：使用无效信息维护高速缓存一致性的片上网络
公开(公告)号：US08473667B2
公开(公告)日：2013-06-25
申请号：US11972753
申请日：2008-01-11
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F12/0808 , G06F12/0815
摘要： A network on chip (‘NOC’), and methods of operation of a NOC, that maintains cache coherency with invalidation messages, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including an invalidating module configured to send, to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory and the selected IP blocks, each selected IP block configured to invalidate the contents of the cached memory responsive to receiving the invalidation message.
摘要翻译：一个片上网络（NOC），以及NOC的操作方法，通过无效消息来保持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器 IP块通过存储器通信控制器和网络接口控制器适配于路由器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括无效模块，其被配置为向所选择的IP块发送无效消息，所述无效消息表示使缓存的存储器和所选择的IP块无效的指令，每个所选择的IP块被配置为响应于接收到所述无效消息而使所缓存的存储器的内容无效。

7. 发明申请

US20130044117A1 VECTOR REGISTER FILE CACHING OF CONTEXT DATA STRUCTURE FOR MAINTAINING STATE DATA IN A MULTITHREADED IMAGE PROCESSING PIPELINE 有权
标题翻译：用于维护多图像处理管道中状态数据的上下文数据结构的矢量寄存器文件
公开(公告)号：US20130044117A1
公开(公告)日：2013-02-21
申请号：US13212418
申请日：2011-08-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T1/20 , G06F9/02 , G06F15/76
CPC分类号： G06F9/30 , G06F9/38 , G06F9/383 , G06T1/20
摘要： Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.
摘要翻译：在多线程图形处理架构中使用的经常访问的状态数据被缓存在处理单元的向量寄存器文件中，以优化对状态数据的访问并最小化与其相关联的存储器总线利用。处理单元可以包括固定点执行单元以及向量浮点执行单元，并且向量浮点执行单元使用的向量寄存器文件可用于对由固定点执行单元使用的状态数据进行缓存并转移为需要进入由固定点执行单元访问的通用寄存器，从而减少了从固定点执行单元访问的L1或更低级高速缓存重复检索和回写状态数据的需要。

8. 发明申请

US20120176364A1 REUSE OF STATIC IMAGE DATA FROM PRIOR IMAGE FRAMES TO REDUCE RASTERIZATION REQUIREMENTS 失效
标题翻译：从先前的图像框架中减少静态图像数据以减少放射性要求
公开(公告)号：US20120176364A1
公开(公告)日：2012-07-12
申请号：US12985607
申请日：2011-01-06
申请人： Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Eric O. Mejdrich
发明人： Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Eric O. Mejdrich
IPC分类号： G06T15/00
CPC分类号： G09G5/393 , G06T1/60 , G06T15/005 , G06T15/20 , G06T15/405 , G09G5/39
摘要： An apparatus, program product and method reuse static image data generated during rasterization of static geometry to reduce the processing overhead associated with rasterizing subsequent image frames. In particular, static image data generated one frame may be reused in a subsequent image frame such that the subsequent image frame is generated without having to re-rasterize the static geometry from the scene, i.e., with only the dynamic geometry rasterized. The resulting image frame includes dynamic image data generated as a result of rasterizing the dynamic geometry during that image frame, and static image data generated as a result of rasterizing the static image data during a prior image frame.
摘要翻译：一种装置，程序产品和方法重用在静态几何的光栅化期间产生的静态图像数据，以减少与后续图像帧的光栅化相关联的处理开销。特别地，生成一帧的静态图像数据可以在随后的图像帧中重新使用，使得生成后续图像帧，而不必从场景重新光栅化静态几何，即仅光栅化动态几何。所得到的图像帧包括作为在该图像帧期间光栅化动态几何结果而生成的动态图像数据，以及作为在先前图像帧期间对静态图像数据进行光栅化而产生的静态图像数据。

9. 发明授权

US08078850B2 Branch prediction technique using instruction for resetting result table pointer 有权
标题翻译：分支预测技术，使用指令重置结果表指针
公开(公告)号：US08078850B2
公开(公告)日：2011-12-13
申请号：US12108846
申请日：2008-04-24
申请人： Jamie R. Kuesel , Mark G. Kupferschmidt , Eric O. Mejdrich , Paul E. Schardt
发明人： Jamie R. Kuesel , Mark G. Kupferschmidt , Eric O. Mejdrich , Paul E. Schardt
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3844 , G06F9/30145 , G06F9/322 , G06F9/3806
摘要： Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.
摘要翻译：公开了一种用于在计算机处理器中进行分支预测的方法，装置和产品，包括：在分支出现多于一次的算法中记录分支出现次序，每个分支的结果包括保持指针到最近记录的结果的位置; 完成算法后，将指针复位到第一记录结果的位置; 并根据记录的结果预测分支的随后的分支结果。

10. 发明授权

US08020168B2 Dynamic virtual software pipelining on a network on chip 失效
标题翻译：在芯片上的动态虚拟软件流水线
公开(公告)号：US08020168B2
公开(公告)日：2011-09-13
申请号：US12117897
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/76 , G06F9/46
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译：一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。

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