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1. 发明授权

US07504867B2 Bus holders having wide input and output voltage ranges and tolerant input/output buffers using the same 失效
标题翻译：总线保持器具有宽输入和输出电压范围，并且使用相同的容限输入/输出缓冲器
公开(公告)号：US07504867B2
公开(公告)日：2009-03-17
申请号：US11341142
申请日：2006-01-27
申请人： Jae-Bum Choi , Eon-Guk Kim
发明人： Jae-Bum Choi , Eon-Guk Kim
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K3/0375 , H03K5/086
摘要： A bus holder includes a first inverter, a second inverter and a pass switch. The first inverter is coupled between a first power supply voltage node and a second power supply voltage node, and receives an input signal via an input terminal to output a first output signal having an inverted phase with respect to the input signal. The second inverter is coupled between the first power supply voltage node and the second power supply voltage node, and inverts the first output signal to output a second output signal, having an inverted phase with respect to the first output signal, to an output terminal. The pass switch is coupled between the input terminal and the output terminal, and outputs a signal having a level of a control voltage to the input terminal, in response to the control voltage. Accordingly, a tolerant input/output buffer may stably maintain an input signal level when a bus is floated.
摘要翻译：总线保持器包括第一反相器，第二反相器和通过开关。第一反相器耦合在第一电源电压节点和第二电源电压节点之间，并且经由输入端子接收输入信号，以输出相对于输入信号具有反相的第一输出信号。第二反相器耦合在第一电源电压节点和第二电源电压节点之间，并且将第一输出信号反相以将具有相对于第一输出信号的反相的第二输出信号输出到输出端。通过开关耦合在输入端子和输出端子之间，并且响应于控制电压而将具有控制电压电平的信号输出到输入端子。因此，当总线浮动时，容限输入/输出缓冲器可以稳定地保持输入信号电平。

2. 发明申请

US20080036490A1 Semiconductor integrated circuit device with a fail-safe IO circuit and electronic device including the same 有权
标题翻译：具有故障保护IO电路的半导体集成电路装置和包括其的电子装置
公开(公告)号：US20080036490A1
公开(公告)日：2008-02-14
申请号：US11826312
申请日：2007-07-13
申请人： Dae Gyu Kim , Eon Guk Kim , Ju Young Kim
发明人： Dae Gyu Kim , Eon Guk Kim , Ju Young Kim
IPC分类号： H03K19/007
CPC分类号： H03K19/007
摘要： A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.
摘要翻译：半导体IC器件包括至少一个IO端口，核心逻辑和至少一个故障保护IO电路，故障安全IO电路耦合在核心逻辑和IO端口之间，其中故障安全IO电路是被配置为接收预定的控制信号并且将IO端口相对于预定的控制信号保持在预定的阻抗。

3. 发明申请

US20060181315A1 Bus holders having wide input and output voltage ranges and tolerant input/output buffers using the same 失效
公开(公告)号：US20060181315A1
公开(公告)日：2006-08-17
申请号：US11341142
申请日：2006-01-27
申请人： Jae-Bum Choi , Eon-Guk Kim
发明人： Jae-Bum Choi , Eon-Guk Kim
IPC分类号： H03B1/00
CPC分类号： H03K3/0375 , H03K5/086
摘要： A bus holder includes a first inverter, a second inverter and a pass switch. The first inverter is coupled between a first power supply voltage node and a second power supply voltage node, and receives an input signal via an input terminal to output a first output signal having an inverted phase with respect to the input signal. The second inverter is coupled between the first power supply voltage node and the second power supply voltage node, and inverts the first output signal to output a second output signal, having an inverted phase with respect to the first output signal, to an output terminal. The pass switch is coupled between the input terminal and the output terminal, and outputs a signal having a level of a control voltage to the input terminal, in response to the control voltage. Accordingly, a tolerant input/output buffer may stably maintain an input signal level when a bus is floated.

4. 发明授权

US08154323B2 Output driver operable over wide range of voltages 有权
标题翻译：输出驱动器可在宽电压范围内工作
公开(公告)号：US08154323B2
公开(公告)日：2012-04-10
申请号：US12771034
申请日：2010-04-30
申请人： Eon-guk Kim , Dae-gyu Kim
发明人： Eon-guk Kim , Dae-gyu Kim
IPC分类号： H03B1/00
CPC分类号： H03K3/356113 , H03K19/018521
摘要： An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.
摘要翻译：输出驱动器包括耦合到输出端子的上拉电路和下拉电路以及具有耦合到上拉电路的P沟道晶体管的栅极端子的第一端子的电容器，以及配置成接收驱动信号。输出驱动器还包括耦合到电容器的第一端子并且被配置为当驱动信号处于信号接地电压时将电荷从电源节点传递到电容器的第一端子的驱动电路，并且将电荷的第一端子当驱动信号处于大于信号接地电压的电压电平时，来自电源节点的电容器，使得在P沟道晶体管的栅极端产生的信号的电压摆幅被限制为小于电源节点相对于信号接地电压。

5. 发明授权

US07656185B2 Semiconductor integrated circuit device with a fail-safe IO circuit and electronic device including the same 有权
标题翻译：具有故障保护IO电路的半导体集成电路装置和包括其的电子装置
公开(公告)号：US07656185B2
公开(公告)日：2010-02-02
申请号：US11826312
申请日：2007-07-13
申请人： Dae Gyu Kim , Eon Guk Kim , Ju Young Kim
发明人： Dae Gyu Kim , Eon Guk Kim , Ju Young Kim
IPC分类号： H03K19/007
CPC分类号： H03K19/007
摘要： A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.
摘要翻译：半导体IC器件包括至少一个IO端口，核心逻辑和至少一个故障保护IO电路，故障安全IO电路耦合在核心逻辑和IO端口之间，其中故障安全IO电路是被配置为接收预定的控制信号并且将IO端口相对于预定的控制信号保持在预定的阻抗。

6. 发明授权

US07388410B2 Input circuits configured to operate using a range of supply voltages 失效
标题翻译：配置为使用一系列电源电压进行操作的输入电路
公开(公告)号：US07388410B2
公开(公告)日：2008-06-17
申请号：US11350711
申请日：2006-02-09
申请人： Eon-Guk Kim , Dae-Gyu Kim , Jae-Bum Choi
发明人： Eon-Guk Kim , Dae-Gyu Kim , Jae-Bum Choi
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/0013 , H03K3/3565
摘要： An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response to the first transmission signal. The input signal transmission circuit includes a voltage drop element connected to the input node and configured to provide a voltage drop between the input node and a transistor having a gate to which a first supply voltage is applied. An input circuit may include an input signal transmission circuit configured to output a first transmission signal in response to an input signal and a feedback control signal, a Schmitt trigger inverter configured to output a second transmission signal in response to the first transmission signal and a second control signal, and an enable block configured to generate the feedback control signal and the second control signal in response to an enable signal.
摘要翻译：输入电路包括输入信号传输电路，其被配置为响应于输入节点处的输入信号而在第一输出节点处输出第一传输信号，施密特触发器反相器被配置为在第二输出节点处输出第二传输信号响应于第一传输信号。输入信号传输电路包括连接到输入节点并被配置为在输入节点和具有施加了第一电源电压的栅极的晶体管之间提供电压降的电压降单元。输入电路可以包括输入信号传输电路，其被配置为响应于输入信号和反馈控制信号输出第一传输信号，施密特触发器反相器被配置为响应于第一传输信号输出第二传输信号，第二传输信号控制信号以及响应于使能信号产生反馈控制信号和第二控制信号的使能块。

7. 发明申请

US20060181322A1 Input circuits configured to operate using a range of supply voltages 失效
标题翻译：配置为使用一系列电源电压进行操作的输入电路
公开(公告)号：US20060181322A1
公开(公告)日：2006-08-17
申请号：US11350711
申请日：2006-02-09
申请人： Eon-Guk Kim , Dae-Gyu Kim , Jae-Bum Choi
发明人： Eon-Guk Kim , Dae-Gyu Kim , Jae-Bum Choi
IPC分类号： H03K3/037
CPC分类号： H03K19/0013 , H03K3/3565
摘要： An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response to the first transmission signal. The input signal transmission circuit includes a voltage drop element connected to the input node and configured to provide a voltage drop between the input node and a transistor having a gate to which a first supply voltage is applied. An input circuit may include an input signal transmission circuit configured to output a first transmission signal in response to an input signal and a feedback control signal, a Schmitt trigger inverter configured to output a second transmission signal in response to the first transmission signal and a second control signal, and an enable block configured to generate the feedback control signal and the second control signal in response to an enable signal.
摘要翻译：输入电路包括输入信号传输电路，其被配置为响应于输入节点处的输入信号而在第一输出节点处输出第一传输信号，施密特触发器反相器被配置为在第二输出节点处输出第二传输信号响应于第一传输信号。输入信号传输电路包括连接到输入节点并被配置为在输入节点和具有施加了第一电源电压的栅极的晶体管之间提供电压降的电压降单元。输入电路可以包括输入信号传输电路，其被配置为响应于输入信号和反馈控制信号输出第一传输信号，施密特触发器反相器被配置为响应于第一传输信号输出第二传输信号，第二传输信号控制信号以及响应于使能信号产生反馈控制信号和第二控制信号的使能块。

8. 发明申请

US20110025380A1 OUTPUT DRIVER OPERABLE OVER WIDE RANGE OF VOLTAGES 有权
标题翻译：输出驱动器可以在宽电压范围内工作
公开(公告)号：US20110025380A1
公开(公告)日：2011-02-03
申请号：US12771034
申请日：2010-04-30
申请人： Eon-guk Kim , Dae-gyu Kim
发明人： Eon-guk Kim , Dae-gyu Kim
IPC分类号： H03K3/00
CPC分类号： H03K3/356113 , H03K19/018521
摘要： An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.
摘要翻译：输出驱动器包括耦合到输出端子的上拉电路和下拉电路以及具有耦合到上拉电路的P沟道晶体管的栅极端子的第一端子的电容器，以及配置成接收驱动信号。输出驱动器还包括耦合到电容器的第一端子并且被配置为当驱动信号处于信号接地电压时将电荷从电源节点传递到电容器的第一端子的驱动电路，并且将电荷的第一端子当驱动信号处于大于信号接地电压的电压电平时，来自电源节点的电容器，使得在P沟道晶体管的栅极端产生的信号的电压摆幅被限制为小于电源节点相对于信号接地电压。

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