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1. 发明授权

US06526562B1 Methods for developing an integrated circuit chip design 有权
标题翻译：开发集成电路芯片设计的方法
公开(公告)号：US06526562B1
公开(公告)日：2003-02-25
申请号：US09568398
申请日：2000-05-10
申请人： Elie Haddad , James Monaco , Thomas Tomazin , William C. Anderson
发明人： Elie Haddad , James Monaco , Thomas Tomazin , William C. Anderson
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A method for developing an integrated circuit chip design includes the steps of developing an architecture specification defining the functions of the chip, developing a microarchitecture specification based on the architecture specification, developing a functional and structural model of the chip based on the microarchitecture specification, designing software tools for use with the chip based on the architecture specification, and designing chip verification tools based on the microarchitecture specification. The activities associated with chip development are divided into phases which may be performed concurrently. The result of the development is an RTL model of the chip which can be utilized in implementation of products without comprising proprietary circuit, layout and fabrication process information of the entity that is implementing the products.
摘要翻译：一种用于开发集成电路芯片设计的方法包括以下步骤：开发定义芯片功能的架构规范，基于架构规范开发微架构规范，基于微架构规范开发芯片的功能和结构模型，设计基于架构规范与芯片一起使用的软件工具，以及基于微架构规范设计芯片验证工具。与芯片开发相关的活动分为可以同时执行的阶段。开发的结果是芯片的RTL模型，可以用于实现产品，而不包括正在实施产品的实体的专有电路，布局和制造过程信息。

2. 发明授权

US4996641A Diagnostic mode for a cache 失效
标题翻译：缓存的诊断模式
公开(公告)号：US4996641A
公开(公告)日：1991-02-26
申请号：US181856
申请日：1988-04-15
申请人： Yoav Talgam , Paul A. Reed , Elie Haddad , James A. Klingshirn
发明人： Yoav Talgam , Paul A. Reed , Elie Haddad , James A. Klingshirn
IPC分类号： G06F11/22 , G06F12/08 , G06F12/12 , G06F12/16 , G11C29/00 , G11C29/24 , G06F11/10
CPC分类号： G11C29/88 , G06F12/0888 , G11C29/24
摘要： A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing TAG addresses. The hit signal is not generated unless a TAG address corresponds to the address received on the address bus. Associated with each TAG location are valid bits, disable bits, and LRU bits. The requested data is contained in data locations in the cache. Each data location has a corresponding TAG location. The disable bits can be set under the control of the processor for the case where a data location is defective. Additionally, in various diagnostic modes, the TAG locations, the valid bits, the LRU bits, and the data locations are directly accessible via the data bus.

3. 发明授权

US2355372A Grinding wheel forming and dressing means 失效
标题翻译：砂轮成型和修整手段
公开(公告)号：US2355372A
公开(公告)日：1944-08-08
申请号：US52307944
申请日：1944-02-19
申请人： ELIE HADDAD
发明人： ELIE HADDAD
IPC分类号： B24B53/08
CPC分类号： B24B53/081

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