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1. 发明授权

US07705423B2 Device having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry of an integrated circuit 失效
标题翻译：具有用于功率传递和集成电路的高速输入/输出电路的去耦的嵌入式电容器阵列的器件
公开(公告)号：US07705423B2
公开(公告)日：2010-04-27
申请号：US11523270
申请日：2006-09-19
申请人： Madhavan Swaminathan , Ege Engin , Prathap Muthana , Krishna Srinivasan
发明人： Madhavan Swaminathan , Ege Engin , Prathap Muthana , Krishna Srinivasan
IPC分类号： H01L29/00
CPC分类号： H01L23/66 , H01L23/49822 , H01L23/50 , H01L2224/16 , H01L2924/3011 , H05K1/162 , H05K2201/09763 , H05K2201/10674 , Y10S257/924
摘要： One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.
摘要翻译：本发明的一个实施例提供了向包括半导体管芯，输入/输出电源端子以及选自离散，平面和组合的嵌入式陶瓷电容器阵列的集成电路提供低噪声电源封装的建议，其中所述电容器被放置在从半导体管芯的阴影的周边中选择的位置，部分地在半导体管芯的阴影的周边内，靠近半导体管芯的阴影的周边，以及它们的组合。

2. 发明授权

US07504706B2 Packaging having an array of embedded capacitors for power delivery and decoupling in the mid-frequency range and methods of forming thereof 失效
标题翻译：封装具有用于在中频范围内进行功率输送和去耦的嵌入式电容器阵列及其形成方法
公开(公告)号：US07504706B2
公开(公告)日：2009-03-17
申请号：US11514097
申请日：2006-08-31
申请人： Madhavan Swaminathan , Ege Engin , Lixi Wan , Prathap Muthana
发明人： Madhavan Swaminathan , Ege Engin , Lixi Wan , Prathap Muthana
IPC分类号： H01L29/00
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/50 , H01L23/66 , H01L2924/0002 , H01L2924/15311 , H01L2924/3011 , H05K3/429 , H05K3/4602 , H05K2201/09309 , H05K2201/09509 , H05K2201/09536 , H05K2201/09618 , H05K2201/09763 , Y10S257/904 , Y10S257/924 , H01L2924/00
摘要： One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.
摘要翻译：本发明的一个实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括在所述封装中安装嵌入式分立陶瓷电容器阵列，以及可选的平面电容层。另一实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括具有不同谐振频率的嵌入式分立陶瓷电容器阵列，其布置成使得电容器阵列在关键中频范围内的阻抗与频率曲线产生等于或低于目标阻抗值的阻抗值。

3. 发明授权

US07895540B2 Multilayer finite difference methods for electrical modeling of packages and printed circuit boards 有权
标题翻译：封装和印刷电路板电气建模的多层有限差分法
公开(公告)号：US07895540B2
公开(公告)日：2011-02-22
申请号：US11888705
申请日：2007-08-02
申请人： Ege Engin , Madhavan Swaminathan
发明人： Ege Engin , Madhavan Swaminathan
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5018 , G06F2217/78
摘要： Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit models for such single plane pairs based on multilayer finite difference approximation. Based on the methods, coupling between different layers through electrically large apertures can be modeled very accurately and efficiently.
摘要翻译：公开了用于电磁模拟平面多层结构的示例性有限差分法。示例性的有限差分法通过组合单平面对的导纳矩阵和基于多层有限差分近似的单平面对的等效电路模型来模拟多层平面。基于这些方法，可以非常准确和有效地建模通过电气大孔的不同层之间的耦合。

4. 发明申请

US20100218145A1 Multilayer finite difference methods for electrical modeling of packages and printed circuit boards 有权
标题翻译：封装和印刷电路板电气建模的多层有限差分法
公开(公告)号：US20100218145A1
公开(公告)日：2010-08-26
申请号：US11888705
申请日：2007-08-02
申请人： Ege Engin , Madhavan Swaminathan
发明人： Ege Engin , Madhavan Swaminathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/78
摘要： Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit models for such single plane pairs based on multilayer finite difference approximation. Based on the methods, coupling between different layers through electrically large apertures can be modeled very accurately and efficiently.
摘要翻译：公开了用于电磁模拟平面多层结构的示例性有限差分法。示例性的有限差分法通过组合单平面对的导纳矩阵和基于多层有限差分近似的单平面对的等效电路模型来模拟多层平面。基于这些方法，可以非常准确和有效地建模通过电气大孔的不同层之间的耦合。

5. 发明申请

US20080091389A1 SYSTEMS AND METHODS FOR ELECTROMAGNETIC BAND GAP STRUCTURE SYNTHESIS 有权
标题翻译：电磁带隙结构合成的系统与方法
公开(公告)号：US20080091389A1
公开(公告)日：2008-04-17
申请号：US11854997
申请日：2007-09-13
申请人： Tae Hong Kim , Ege Engin , Madhavan Swaminathan
发明人： Tae Hong Kim , Ege Engin , Madhavan Swaminathan
IPC分类号： G06F17/10
CPC分类号： G06F17/5068
摘要： The present invention describes methods and apparatus for electromagnetic band gap structure synthesis. An exemplary embodiment of the present invention provides a method of electromagnetic band gap structure synthesis, which includes the step of providing a set of desired characteristics for an electromagnetic band gap structure. Furthermore, the method includes generating populations of patch shape members with a genetic algorithm routine and solving one or more of patch shape members of the populations with an electrodynamics modeling technique. Thereafter, the method includes the step of converting the output of the electrodynamics modeling technique into a set of response data for one or more of the patch shape members and calculating a fitness level for one or more of the sets of response data in comparison to the set of desired characteristics for the electromagnetic band gap structure. Next, the method includes the step of determining whether the fitness level of one of the patch shape members is within a predetermined tolerance. Subsequently, if none of the patch shape members provides a fitness level within the predetermined tolerance, then the steps of generating, solving, converting, calculating, and determining are repeated.
摘要翻译：本发明描述了用于电磁带隙结构合成的方法和装置。本发明的一个示例性实施例提供了一种电磁带隙结构合成方法，其包括为电磁带隙结构提供一组所需特性的步骤。此外，该方法包括使用遗传算法程序生成斑块形状成员的群体，并用电动力学建模技术解决群体中的一个或多个斑块形状成员。此后，该方法包括以下步骤：将电动力学建模技术的输出转换成用于一个或多个补片形状构件的一组响应数据，并计算一组或多组响应数据的适应度水平，与设置电磁带隙结构的所需特性。接下来，该方法包括以下步骤：确定一个贴片形状构件的适合度是否在预定的容限内。随后，如果贴片形状构件中没有一个在预定公差内提供适合度，则重复生成，求解，转换，计算和确定的步骤。

6. 发明申请

US20070120225A1 Packaging having an array of embedded capacitors for power delivery and decoupling in the mid-frequency range and methods of forming thereof 失效
标题翻译：封装具有用于在中频范围内进行功率输送和去耦的嵌入式电容器阵列及其形成方法
公开(公告)号：US20070120225A1
公开(公告)日：2007-05-31
申请号：US11514097
申请日：2006-08-31
申请人： Madhavan Swaminathan , Ege Engin , Lixi Wan , Prathap Muthana
发明人： Madhavan Swaminathan , Ege Engin , Lixi Wan , Prathap Muthana
IPC分类号： H01L29/93
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/50 , H01L23/66 , H01L2924/0002 , H01L2924/15311 , H01L2924/3011 , H05K3/429 , H05K3/4602 , H05K2201/09309 , H05K2201/09509 , H05K2201/09536 , H05K2201/09618 , H05K2201/09763 , Y10S257/904 , Y10S257/924 , H01L2924/00
摘要： One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising using an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.
摘要翻译：本发明的一个实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括在所述封装中安装嵌入式分立陶瓷电容器阵列，以及可选的平面电容层。另一实施例提供了一种用于在1MHz至3GHz的中频范围内为IC提供低噪声电源封装的装置，其包括使用具有不同谐振频率的嵌入式分立陶瓷电容器阵列，其布置成使得电容阵列的阻抗与临界中频范围内的频率曲线产生等于或低于目标阻抗值的阻抗值。

7. 发明授权

US08060457B2 Systems and methods for electromagnetic band gap structure synthesis 有权
标题翻译：电磁带隙结构合成的系统和方法
公开(公告)号：US08060457B2
公开(公告)日：2011-11-15
申请号：US11854997
申请日：2007-09-13
申请人： Tae Hong Kim , Ege Engin , Madhavan Swaminathan
发明人： Tae Hong Kim , Ege Engin , Madhavan Swaminathan
IPC分类号： G06F15/18 , G06N3/00 , G06N3/12
CPC分类号： G06F17/5068
摘要： The present invention describes methods and apparatus for electromagnetic band gap structure synthesis. An exemplary embodiment of the present invention provides a method of electromagnetic band gap structure synthesis, which includes the step of providing a set of desired characteristics for an electromagnetic band gap structure. Furthermore, the method includes generating populations of patch shape members with a genetic algorithm routine and solving one or more of patch shape members of the populations with an electrodynamics modeling technique. Thereafter, the method includes the step of converting the output of the electrodynamics modeling technique into a set of response data for one or more of the patch shape members and calculating a fitness level for one or more of the sets of response data in comparison to the set of desired characteristics for the electromagnetic band gap structure. Next, the method includes the step of determining whether the fitness level of one of the patch shape members is within a predetermined tolerance. Subsequently, if none of the patch shape members provides a fitness level within the predetermined tolerance, then the steps of generating, solving, converting, calculating, and determining are repeated.
摘要翻译：本发明描述了用于电磁带隙结构合成的方法和装置。本发明的一个示例性实施例提供了一种电磁带隙结构合成方法，其包括为电磁带隙结构提供一组所需特性的步骤。此外，该方法包括使用遗传算法程序生成斑块形状成员的群体，并用电动力学建模技术解决群体中的一个或多个斑块形状成员。此后，该方法包括以下步骤：将电动力学建模技术的输出转换成用于一个或多个补片形状构件的一组响应数据，并计算一组或多组响应数据的适应度水平，与设置电磁带隙结构的所需特性。接下来，该方法包括以下步骤：确定一个贴片形状构件的适合度是否在预定的容限内。随后，如果贴片形状构件中没有一个在预定公差内提供适合度，则重复生成，求解，转换，计算和确定的步骤。

8. 发明申请

US20070102811A1 Package having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuit and methods of forming thereof 失效
标题翻译：具有用于高速输入/输出电路的功率输送和去耦的嵌入式电容器阵列的封装及其形成方法
公开(公告)号：US20070102811A1
公开(公告)日：2007-05-10
申请号：US11523270
申请日：2006-09-19
申请人： Madhavan Swaminathan , Ege Engin , Prathap Muthana , Krishna Srinivasan
发明人： Madhavan Swaminathan , Ege Engin , Prathap Muthana , Krishna Srinivasan
IPC分类号： H01L23/04
CPC分类号： H01L23/66 , H01L23/49822 , H01L23/50 , H01L2224/16 , H01L2924/3011 , H05K1/162 , H05K2201/09763 , H05K2201/10674 , Y10S257/924
摘要： One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.
摘要翻译：本发明的一个实施例提供了向包括半导体管芯，输入/输出电源端子以及选自离散，平面和组合的嵌入式陶瓷电容器阵列的集成电路提供低噪声电源封装的建议，其中所述电容器被放置在从半导体管芯的阴影的周边中选择的位置，部分地在半导体管芯的阴影的周边内，靠近半导体管芯的阴影的周边，以及它们的组合。

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