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1. 发明申请

US20100163888A1 MANUFACTURING PROCESS OF A POWER ELECTRONIC DEVICE INTEGRATED IN A SEMICONDUCTOR SUBSTRATE WITH WIDE BAND GAP AND ELECTRONIC DEVICE THUS OBTAINED 有权
标题翻译：集成在具有宽带隙的半导体衬底和获得的电子器件的功率电子器件的制造过程
公开(公告)号：US20100163888A1
公开(公告)日：2010-07-01
申请号：US12641146
申请日：2009-12-17
申请人： Mario Giuseppe SAGGIO , Edoardo ZANETTI , Ferruccio FRISINA
发明人： Mario Giuseppe SAGGIO , Edoardo ZANETTI , Ferruccio FRISINA
IPC分类号： H01L29/24 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7811 , H01L21/0485 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0696 , H01L29/1608 , H01L29/402 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/66666 , H01L29/7802
摘要： An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.
摘要翻译：一种用于制造具有第一导电类型的具有宽禁带隙的材料的半导体本体上的电子器件的方法的实施例。该方法包括以下步骤：在半导体本体上形成第一掩模，该第一掩模在半导体本体的第一表面部分和第二表面部分之上具有第一窗口和第二窗口; 在第一和第二窗口下面的半导体本体的第一和第二表面部分内形成具有第二导电类型的至少一个第一导电区域和一个第二导电区域，第一导电区域和第二导电区域彼此面对; 在所述半导体主体上形成第二掩模，所述第二掩模在所述第一导电区域和所述第二导电区域的表面部分上方具有多个窗口; 在所述第一导电区域和所述第二导电区域内以及所述多个窗口下方形成具有所述第一导电类型的多个第三导电区域; 彻底清除第一和第二掩模; 在高温下进行第一，第二和第三导电区域的激活热处理; 并形成体和源区。

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