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1. 发明专利

TW200504819A 室溫之金屬導引結合 ROOM TEMPERATURE METAL DIRECT BONDING 审中-公开
简体标题：室温之金属导引结合 ROOM TEMPERATURE METAL DIRECT BONDING
公开(公告)号：TW200504819A
公开(公告)日：2005-02-01
申请号：TW093102781
申请日：2004-02-06
申请人：童勤義 TONG, QIN-YI , 安東尼S 羅斯 ROSE, ANTHONY S , 保羅M. 因昆斯特 ENQUIST, PAUL M
发明人：童勤義 TONG, QIN YI , 安東尼S 羅斯 ROSE, ANTHONY S , 保羅M. 因昆斯特 ENQUIST, PAUL M
IPC分类号： H01L
CPC分类号： H01L21/76251 , B23K20/02 , H01L21/481 , H01L24/09 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/28 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/89 , H01L24/90 , H01L25/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/13011 , H01L2224/13099 , H01L2224/13109 , H01L2224/13144 , H01L2224/13147 , H01L2224/32145 , H01L2224/80801 , H01L2224/81011 , H01L2224/81013 , H01L2224/81014 , H01L2224/81136 , H01L2224/81143 , H01L2224/81193 , H01L2224/81208 , H01L2224/8121 , H01L2224/81801 , H01L2224/81815 , H01L2224/8183 , H01L2224/81894 , H01L2224/83095 , H01L2224/8319 , H01L2224/8334 , H01L2224/83801 , H01L2224/8383 , H01L2224/8384 , H01L2224/8385 , H01L2224/83894 , H01L2224/83895 , H01L2224/83907 , H01L2224/9202 , H01L2225/06513 , H01L2924/00013 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/0106 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/1532 , H01L2924/351 , Y10T29/49126 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/05644 , H01L2924/00014 , H01L2224/05664 , H01L2224/05669 , H01L2224/05124 , H01L2224/05147
摘要：一結合元件結構，包括一第一基材，其具有一較佳連接至一元件或電路之第一組金屬結合墊，且具有一與第一基材上的金屬結合墊相鄰之第一非金屬區；一第二基材，其具有一對準於第一組金屬結合墊且較佳連接至一元件或電路之第二組金屬結合墊，且具有一與第二基材上的金屬結合墊相鄰之第二非金屬區；及一接觸結合介面，其位於藉由將第一非金屬區接觸結合至第二非金屬區所形成之第一及第二組金屬結合墊之間。第一及第二基材的至少一者可彈性變形。
简体摘要：一结合组件结构，包括一第一基材，其具有一较佳连接至一组件或电路之第一组金属结合垫，且具有一与第一基材上的金属结合垫相邻之第一非金属区；一第二基材，其具有一对准于第一组金属结合垫且较佳连接至一组件或电路之第二组金属结合垫，且具有一与第二基材上的金属结合垫相邻之第二非金属区；及一接触结合界面，其位于借由将第一非金属区接触结合至第二非金属区所形成之第一及第二组金属结合垫之间。第一及第二基材的至少一者可弹性变形。

2. 发明申请

WO2005091868A2 WAFER SCALE DIE HANDLING 审中-公开
公开(公告)号：WO2005091868A2
公开(公告)日：2005-10-06
申请号：PCT/US2005/005641
申请日：2005-02-23
申请人： ZIPTRONIX, INC. , ENQUIST, Paul, M. , FOUNTAIN, Gaius, G., Jr. , PETTEWAY, Carl, T.
发明人： ENQUIST, Paul, M. , FOUNTAIN, Gaius, G., Jr. , PETTEWAY, Carl, T.
IPC分类号： H01L23/495
CPC分类号： H01L21/67333 , H01L2924/0002 , Y10S414/135 , Y10S414/14 , Y10S414/141 , H01L2924/00
摘要： A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.
摘要翻译：一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。该元件与半导体晶片处理设备和/或半导体晶片处理兼容。优选地，构件容纳来自半导体晶片的至少大部分管芯。此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置去除管芯，将来自单个瓦楞纸包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将放置在半导体封装中以形成集成电路。提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将放置在半导体封装中以形成集成电路。

3. 发明申请

WO2005043584A2 SINGLE MASK VIA METHOD AND DEVICE 审中-公开
标题翻译：通过方法和设备的单面罩
公开(公告)号：WO2005043584A2
公开(公告)日：2005-05-12
申请号：PCT/US2004/032312
申请日：2004-10-20
申请人： ZIPTRONIX, INC. , ENQUIST, Paul, M.
发明人： ENQUIST, Paul, M.
IPC分类号： H01L
CPC分类号： H01L25/0657 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/83 , H01L24/94 , H01L25/0655 , H01L25/50 , H01L2221/68354 , H01L2224/83894 , H01L2224/94 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01049 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/0132 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2224/83 , H01L2924/01015 , H01L2924/01031
摘要： ABSTRACT: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.
摘要翻译：摘要：连接诸如半导体器件的元件和具有诸如半导体器件的连接元件的器件的方法。具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。使用单个掩模在第一元件中形成通孔以暴露第一触点和第二触点。第一接触结构用作掩模以暴露第二接触结构。接触构件形成为与第一和第二接触结构接触。第一接触结构可以具有孔或间隙，第一和第二接触结构通过该孔或间隙连接。第一接触结构的后表面可能被蚀刻暴露。

4. 发明申请

WO2007021639A2 3D IC METHOD AND DEVICE 审中-公开
标题翻译： 3D IC方法和设备
公开(公告)号：WO2007021639A2
公开(公告)日：2007-02-22
申请号：PCT/US2006/030703
申请日：2006-08-07
申请人： ZIPTRONIX, INC. , ENQUIST, Paul, M. , FOUNTAIN, Gaius, Gillman, Jr. , TONG, Qin-Yi
发明人： ENQUIST, Paul, M. , FOUNTAIN, Gaius, Gillman, Jr. , TONG, Qin-Yi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81
摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.
摘要翻译：三维集成元件如单模或晶片的方法以及具有连接元件如单个模具或晶片的集成结构。芯片和晶片中的任一个或两者可以具有形成在其中的半导体器件。具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。第一和第二接触结构可以在结合时暴露，并且由于接合而电连接。可以在接合之后蚀刻和填充通孔，以暴露并形成互连的第一和第二接触结构的电互连，并提供从表面到该互连的电接入。或者，第一接触结构和/或第二接触结构在接合时不暴露，并且在接合之后蚀刻并填充通孔以将第一和第二接触结构电互连并且提供对互连的第一和第二接触结构到表面的电接触。此外，器件可以形成在第一衬底中，该器件设置在第一衬底的器件区域中并且具有第一接触结构。通孔可以在结合之前被蚀刻或蚀刻和填充穿过器件区域并进入第一衬底，并且第一衬底被稀释以暴露通孔，或者在结合之后填充通孔。

5. 发明申请

WO2004071700A2 ROOM TEMPERATURE METAL DIRECT BONDING 审中-公开
标题翻译：房间温度金属直接结合
公开(公告)号：WO2004071700A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/002006
申请日：2004-02-06
申请人： ZIPTRONIX, INC. , TONG, Qin-Yi , ENQUIST, Paul, M. , ROSE, Anthony, Scot
发明人： TONG, Qin-Yi , ENQUIST, Paul, M. , ROSE, Anthony, Scot
IPC分类号： B23K
CPC分类号： H01L21/76251 , B23K20/02 , H01L21/481 , H01L24/09 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/28 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/89 , H01L24/90 , H01L25/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/13011 , H01L2224/13099 , H01L2224/13109 , H01L2224/13144 , H01L2224/13147 , H01L2224/32145 , H01L2224/80801 , H01L2224/81011 , H01L2224/81013 , H01L2224/81014 , H01L2224/81136 , H01L2224/81143 , H01L2224/81193 , H01L2224/81208 , H01L2224/8121 , H01L2224/81801 , H01L2224/81815 , H01L2224/8183 , H01L2224/81894 , H01L2224/83095 , H01L2224/8319 , H01L2224/8334 , H01L2224/83801 , H01L2224/8383 , H01L2224/8384 , H01L2224/8385 , H01L2224/83894 , H01L2224/83895 , H01L2224/83907 , H01L2224/9202 , H01L2225/06513 , H01L2924/00013 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/0106 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/1532 , H01L2924/351 , Y10T29/49126 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/05644 , H01L2924/00014 , H01L2224/05664 , H01L2224/05669 , H01L2224/05124 , H01L2224/05147
摘要： A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
摘要翻译：一种粘结器件结构，包括具有第一组金属接合焊盘的第一衬底，优选地连接到器件或电路，并且具有与第一衬底上的金属焊盘相邻的第一非金属区域，第二衬底具有第二衬底一组金属接合焊盘与第一组金属焊盘对准，优选地连接到器件或电路，并且具有与第二衬底上的金属焊盘相邻的第二非金属区域，以及位于第二衬底之间的接触接合界面通过第一非金属区域与第二非金属区域的接触接合形成的第一和第二组金属接合焊盘。第一和第二基板中的至少一个可能弹性变形。

6. 发明申请

WO2014036407A1 HETEROGENEOUS ANNEALING METHOD AND DEVICE 审中-公开
标题翻译：异构退火方法和装置
公开(公告)号：WO2014036407A1
公开(公告)日：2014-03-06
申请号：PCT/US2013/057536
申请日：2013-08-30
申请人： ENQUIST, Paul, M. , FOUNTAIN, Gaius, Gillman, Jr.
发明人： ENQUIST, Paul, M. , FOUNTAIN, Gaius, Gillman, Jr.
IPC分类号： H01L21/30
CPC分类号： H01L25/0657 , H01L21/2007 , H01L21/6835 , H01L21/76898 , H01L23/49866 , H01L24/32 , H01L24/83 , H01L25/50 , H01L2221/68359 , H01L2224/29147 , H01L2224/29155 , H01L2224/83053 , H01L2224/83201 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
摘要翻译：一种将具有第一表面的第一衬底与第一绝缘材料和第一接触结构与具有第二表面的第二衬底与第二绝缘材料和第二接触结构集成的方法。第一绝缘材料直接接合到第二绝缘材料上。去除第一衬底的一部分以留下剩余部分。具有与第一基板的CTE基本相同的热膨胀系数（CTE）的第三基板被结合到剩余部分。粘合的基底被加热以促进第一和第二接触结构之间的电接触。在加热之后移除第三衬底以提供具有可靠电接触的接合结构。

7. 发明申请

WO2007021639A3 3D IC METHOD AND DEVICE 审中-公开
标题翻译： 3D IC方法和设备
公开(公告)号：WO2007021639A3
公开(公告)日：2009-04-30
申请号：PCT/US2006030703
申请日：2006-08-07
申请人： ZIPTRONIX INC , ENQUIST PAUL M , FOUNTAIN GAIUS GILLMAN JR , TONG QIN-YI
发明人： ENQUIST PAUL M , FOUNTAIN GAIUS GILLMAN JR , TONG QIN-YI
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81
摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.
摘要翻译：三维集成元件如单模或晶片的方法以及具有连接元件如单个模具或晶片的集成结构。芯片和晶片中的任一个或两者可以具有形成在其中的半导体器件。具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。第一和第二接触结构可以在结合时暴露，并且由于接合而电连接。可以在接合之后蚀刻和填充通孔，以暴露并形成互连的第一和第二接触结构的电互连，并提供从表面到该互连的电接入。或者，第一接触结构和/或第二接触结构在接合时不暴露，并且在接合之后蚀刻并填充通孔以电互连第一和第二接触结构，并提供对互连的第一和第二接触结构到表面的电接触。此外，器件可以形成在第一衬底中，该器件设置在第一衬底的器件区域中并且具有第一接触结构。通孔可以在结合之前被蚀刻或蚀刻和填充穿过器件区域并进入第一衬底，并且第一衬底被稀释以暴露通孔，或者在结合之后填充通孔。

8. 发明申请

WO2005091868A3 WAFER SCALE DIE HANDLING 审中-公开
公开(公告)号：WO2005091868A3
公开(公告)日：2009-03-26
申请号：PCT/US2005005641
申请日：2005-02-23
申请人： ZIPTRONIX INC , ENQUIST PAUL M , FOUNTAIN GAIUS G JR , PETTEWAY CARL T
发明人： ENQUIST PAUL M , FOUNTAIN GAIUS G JR , PETTEWAY CARL T
IPC分类号： H01L23/495
CPC分类号： H01L21/67333 , H01L2924/0002 , Y10S414/135 , Y10S414/14 , Y10S414/141 , H01L2924/00
摘要： A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.
摘要翻译：一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。该元件与半导体晶片处理设备和/或半导体晶片处理兼容。优选地，构件容纳来自半导体晶片的至少大部分管芯。此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置中去除裸片，将来自单个华夫饼包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将放置在半导体封装中以形成集成电路。提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将放置在半导体封装中以形成集成电路。

9. 发明申请

WO2005043584A3 SINGLE MASK VIA METHOD AND DEVICE 审中-公开
标题翻译：通过方法和设备的单面罩
公开(公告)号：WO2005043584A3
公开(公告)日：2007-07-26
申请号：PCT/US2004032312
申请日：2004-10-20
申请人： ZIPTRONIX INC , ENQUIST PAUL M
发明人： ENQUIST PAUL M
IPC分类号： H01L21/768 , H01L21/98 , H01L23/48 , H01L23/538 , H01L25/065
CPC分类号： H01L25/0657 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L24/83 , H01L24/94 , H01L25/0655 , H01L25/50 , H01L2221/68354 , H01L2224/83894 , H01L2224/94 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01049 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/0132 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2224/83 , H01L2924/01015 , H01L2924/01031
摘要： A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element (11) having a first contact structure (12) is bonded to a second element (18) having a second contact structure (17). A single mask (40) is used to form a via (50) in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member (92) is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap (60) through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.
摘要翻译：连接诸如半导体器件的元件和具有诸如半导体器件的连接元件的器件的方法。具有第一接触结构（12）的第一元件（11）被结合到具有第二接触结构（17）的第二元件（18）上。单个掩模（40）用于在第一元件中形成通孔（50）以暴露第一接触件和第二接触件。第一接触结构用作掩模以暴露第二接触结构。接触构件（92）形成为与第一和第二接触结构接触。第一接触结构可以具有孔或间隙（60），第一和第二接触结构通过该孔或间隙连接。第一接触结构的后表面可能被蚀刻暴露。

10. 发明申请

WO2004071700A3 ROOM TEMPERATURE METAL DIRECT BONDING 审中-公开
标题翻译：房间温度金属直接结合
公开(公告)号：WO2004071700A3
公开(公告)日：2005-04-21
申请号：PCT/US2004002006
申请日：2004-02-06
申请人： ZIPTRONIX INC , TONG QIN-YI , ENQUIST PAUL M , ROSE ANTHONY SCOT
发明人： TONG QIN-YI , ENQUIST PAUL M , ROSE ANTHONY SCOT
IPC分类号： H01L21/60 , H01L21/98 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/76251 , B23K20/02 , H01L21/481 , H01L24/09 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/28 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/89 , H01L24/90 , H01L25/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/13011 , H01L2224/13099 , H01L2224/13109 , H01L2224/13144 , H01L2224/13147 , H01L2224/32145 , H01L2224/80801 , H01L2224/81011 , H01L2224/81013 , H01L2224/81014 , H01L2224/81136 , H01L2224/81143 , H01L2224/81193 , H01L2224/81208 , H01L2224/8121 , H01L2224/81801 , H01L2224/81815 , H01L2224/8183 , H01L2224/81894 , H01L2224/83095 , H01L2224/8319 , H01L2224/8334 , H01L2224/83801 , H01L2224/8383 , H01L2224/8384 , H01L2224/8385 , H01L2224/83894 , H01L2224/83895 , H01L2224/83907 , H01L2224/9202 , H01L2225/06513 , H01L2924/00013 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/0106 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/1532 , H01L2924/351 , Y10T29/49126 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/05644 , H01L2924/00014 , H01L2224/05664 , H01L2224/05669 , H01L2224/05124 , H01L2224/05147
摘要： A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
摘要翻译：一种粘结器件结构，包括具有第一组金属接合焊盘的第一衬底，优选地连接到器件或电路，并且具有与第一衬底上的金属焊盘相邻的第一非金属区域，第二衬底具有第二衬底一组金属接合焊盘与第一组金属焊盘对准，优选地连接到器件或电路，并且具有与第二衬底上的金属焊盘相邻的第二非金属区域，以及位于第二衬底之间的接触接合界面通过第一非金属区域与第二非金属区域的接触接合形成的第一和第二组金属接合焊盘。第一和第二基板中的至少一个可能弹性变形。

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