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1. 发明申请

WO1996004601A1 DEFUZZIFIER FOR HIGH-RESOLUTION FUZZY LOGIC CONTROLLER 审中-公开
标题翻译：去模糊化设备用于高清晰度模糊逻辑控制器
公开(公告)号：WO1996004601A1
公开(公告)日：1996-02-15
申请号：PCT/DE1995000946
申请日：1995-07-18
申请人： SIEMENS AKTIENGESELLSCHAFT , EICHFELD, Herbert
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/00
CPC分类号： G06N7/04 , Y10S706/90
摘要： A defuzzifier applies a maximum process or first or second centre-of-gravity processes. In the maximum process, a first/last maximum value, at which a corresponding aggregated regulation weight has a maximum value, is selected as sharp output value (g) depending on selection signals (FA1, FA2) and aggregated regulation weights ( gamma ), and an actuating signal (ENGARZ) is generated. In the first or second centre-of-gravity processes (COG12), a sharp output value (g) is derived from centre-of-gravity co-ordinates (S nu ) and aggregated regulation weights ( gamma nu ), alone or associated with surface measurement figures (F nu ). Adders (ADD1, ADD2) each associated with a downstream register (Z-reg, N-reg), a multiplier (MULT) and a divider (DIV) are advantageously used for both centre-of-gravity processes, and one of the adders (ADD2) is used to form the actuating signal (ENGARZ) when defuzzification is carried out according to the maximum process.
摘要翻译：本申请的主题涉及一种去模糊化的装置，其中，根据选择信号（FA1，FA2）和聚集的调节权重（γ），无论是在最大处理处相关联的聚集调节权重是最大的第一/最后一级的值，作为一个清晰的输出值（克）选择并形成激活信号（ENGARZ）或，可选地，在从重心坐标（S NU）和聚集的调节权重（伽马NU）的重心方法的第一或第二中心（COG12）单独或另外地与表面的质量数（F NU），尖输出值（克）所形成其中，所述加法器（ADD1，ADD2），每个与下游寄存器（Z-Reg中，N-REG），乘法器（MULT）和分频器（DIV）有利地为第一和重力方法的第二中心的使用和所述加法器中的一个（ ADD2）（以形成激活信号ENGARZ）时，如果根据最大版本的解模糊完成驾驶。

2. 发明申请

WO1995023360A1 SELF-PROGRAMMING CIRCUIT 审中-公开
标题翻译：自编程电路
公开(公告)号：WO1995023360A1
公开(公告)日：1995-08-31
申请号：PCT/DE1995000161
申请日：1995-02-08
申请人： SIEMENS AKTIENGESELLSCHAFT , EICHFELD, Herbert , LEDERLE, Reiner
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G05B13/02
CPC分类号： G06N7/04
摘要： The invention concerns a circuit (SPSA) comprising a processing unit (VE) with an electrically erasable and programmable read-only memory (EEPROM), a classification unit (KE) and an interface unit (EIF) for the read-only memory. The processing unit (VE) reads out of the read-only memory (EEPROM) instructions and/or data which are automatically programmed by the classification unit (KE) and interface unit (EIF) as a function of processing-unit inputs (E) and/or internally generated values (ED, S) and/or processing-unit outputs (A). The processing unit may consist of a fuzzy-logic controller or an ordinary microprocessor. The circuit proposed has the particular advantage that it automatically adapts to differences in the structure of the system with which it is associated (type versatility) and to changes in the system with time (due to ageing or wear, for instance), and the circuit thus has a wider range of applications and ensures optimum performance for a longer period of time.
摘要翻译：本申请的主题涉及一种电路（SPSA），其中处理单元（VE）与电可擦除电可编程只读存储器（EEPROM），一个分类单元（KE）和接口单元（EIF）提供了用于只读存储器，其中所述处理单元（PU ）命令和/或从所述只读存储器（EEPROM），读取数据，其中（由分类单元KE）和接口单元（EIF），这取决于输入值（e）和/或内部值（ED，S）和/或输出值（一）处理单元（VE）的，被独立地编程。该处理单元可以，例如，在一模糊控制器，或还包括一个常规的微处理器。特此实现的优点是，特别是，本发明的布置中，独立地方差（型品种）和时间变化的结构（老化，磨损）适应产品，和该电路装置因此是更通用的，更最佳利用。

3. 发明申请

WO0156166A2 METHOD AND ANALOG-TO-DIGITAL CONVERTER FOR CONVERTING AN ANALOG VOLTAGE INTO AN ARITHMETICAL VALUE 审中-公开
标题翻译：方法和模拟数字转换器用于实现模拟电压为算术值
公开(公告)号：WO0156166A2
公开(公告)日：2001-08-02
申请号：PCT/DE0100036
申请日：2001-01-08
申请人： INFINEON TECHNOLOGIES AG , EICHFELD HERBERT , SAUERBREY JENS
发明人： EICHFELD HERBERT , SAUERBREY JENS
IPC分类号： H03M1/58 , H03M1/54
CPC分类号： H03M1/58
摘要： According to the inventive method for converting an analog voltage (Vi) is applied to a sample and hold capacitor (CS) which is discharged in several steps by at least one discharge capacitor (C1, ... CN) until a predetermined reference voltage (VREF4) is reached. The arithmetical value, preferably the digital value, of the analog voltage (Vi) is calculated from the number of discharge steps, which is exponentially related to the analog voltage (Vi), by means of an exponential function. An analog-to-digital converter for carrying out this method is characterized by a simple construction and low power loss.
摘要翻译：为了实现模拟电压Vi成算术，优选的数字值的模拟电压（六）到取样与保持电容器（CS）中的至少一个放电电容器的多个步骤铺设（C1，... CN）最多可预先确定的基准电压（V REF4）被排出。从放电步骤的数量，这是在相关的模拟电压（VI），算术，模拟电压（VI）的优选的数字值exponentionellen来计算使用的指数函数。一个模拟 - 数字转换器，用于执行该方法的特征在于结构简单，功耗低。

4. 发明申请

WO1995022100A1 DEVICE FOR THE FAST PROCESSING OF SELECTED FUZZY RULES 审中-公开
标题翻译： DEVICE对于选定的模糊规则快速处理
公开(公告)号：WO1995022100A1
公开(公告)日：1995-08-17
申请号：PCT/DE1995000114
申请日：1995-01-25
申请人： SIEMENS AKTIENGESELLSCHAFT , EICHFELD, Herbert , KÜNEMUND, Thomas
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/60
CPC分类号： G05B13/0295 , G06N7/04
摘要： An arrangement in which rules selected in a knowledge base store (KBK) are addressed, in time, before the unselected rules and in which, provided that at least one of the selected rules of the condition section is met, initially only a rough but rapidly found sharp value (CO1, CO1') is formed on the basis of the selected rules and only subsequently is a more precise but more slowly found further sharp value (CO2) obtained on the basis of the unselected rules, whereby the faster speed can be obtained by a smaller number of selected rules and also by the simplified extraction of the sharp value (CO1'). The advantage of the device of the invention lies especially in the fact that selected rules can be defined for extreme situations which can be processed substantially more rapidly than unselected rules for normal operating situations.
摘要翻译：本申请的主题涉及在其中的布置中，在一个知识库存储器（KBM）选择的规则被非选择规则之前，并且其中按时间顺序处理，如果所选择的规则中的至少一个，条件部分成立时，最初仅一个粗糙，但要确定快速清晰值（CO 2）被执行（CO1，CO1“）形成所选择的规则的基础上，然后才，的非选择规则的基础上，更准确但更慢确定的，进一步大幅值，其中由所选择的规则数比较少的更高的速度，但可以由尖锐值（CO1“）的简化计算来也表示。本发明的设备的优点在于特别是在所选择的规则可以用于极端情况下，这被处理为比在正常操作条件的非选择的规则快得多来限定。

5. 发明申请

WO1993005471A1 FUZZY LOGIC CONTROLLER WITH OPTIMISED STORAGE ORGANISATION 审中-公开
标题翻译： FUZZY LOGIC控制器与优化存储组织
公开(公告)号：WO1993005471A1
公开(公告)日：1993-03-18
申请号：PCT/DE1992000540
申请日：1992-06-30
申请人： SIEMENS AKTIENGESELLSCHAFT , EICHFELD, Herbert , LÖHNER, Michael
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/60
CPC分类号： G06N7/04 , G05B13/0275 , G06F1/0356 , Y10S706/90
摘要： The invention relates to a fuzzy logic controller in which numbers (NI) for linguistic values of the input signal (II) and first and further parts of input relevance functions (ZL, ZH) of the input signal (I1) can be stored in an input store (I1MEM...14MEM) per input signal, in which the numbers for the linguistic values can be taken via a number multiplexer (MUX1a...MUX4a) to a regulating decoder (RDEC) directly and via incrementation devices (INC1...INC4), in which the regulating decoder supplies addresses for a downstream output store (OMEM) and in which an output signal from the output store (OMEM) can be taken directly and the first and further parts of the input relevance functions can be taken via relevance functions multiplexers (MUX1b...MUX4b) to a minimum-maximum circuit (MINMAX). The fuzzy logic controller of the invention is especially distinguished by the need for very little storage space and is therefore particularly suitable for fuzzy logic controllers with on-chip storage.
摘要翻译：本发明涉及一种模糊逻辑控制器，其中输入信号（II）的语言值的数量（NI）和输入信号（I1）的输入相关函数（ZL，ZH）的第一和另外部分可以存储在输入存储（I1MEM ... 14MEM），其中可以通过号码多路复用器（MUX1a ... MUX4a）直接和通过增量装置（INC1）向调节解码器（RDEC）取得语言值的数字。 ..INC4），其中调节解码器为下游输出存储器（OMEM）提供地址，并且其中可以直接采用来自输出存储器（OMEM）的输出信号，并且输入相关函数的第一和另外部分可以是通过相关功能多路复用器（MUX1b ... MUX4b）到最小最大电路（MINMAX）。本发明的模糊逻辑控制器的特征在于需要非常小的存储空间，因此特别适用于具有片上存储的模糊逻辑控制器。

6. 发明申请

WO1995030186A1 PROCESS FOR PREPARING FOR AND ACCOMPLISHING THE FUZZIFICATION OF A DIGITAL INPUT SIGNAL AT AN INPUT OF A FUZZY PROCESSOR 审中-公开
标题翻译：制备和模糊化的实现在一个模糊处理器装配的输入数字信号的一个入口方法
公开(公告)号：WO1995030186A1
公开(公告)日：1995-11-09
申请号：PCT/DE1995000488
申请日：1995-04-10
申请人： SIEMENS AKTIENGESELLSCHAFT , EICHFELD, Herbert
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/60
CPC分类号： G06N7/04
摘要： A fuzzy processor comprises a fuzzifier which calculates the appurtenance values of the relevant input-appurtenance functions from the digital input signal. To this end, the appurtenance functions must be stored. In order to reduce the storage space needed, especially at a high input signal resolution, it is of advantage to describe the appurtenance functions by shape-determined characteristics like restart points and slopes and store these. To save computing time, the definition range of the input signal is devided into equal segments. In the fuzzifiying process only the segment is considered in which the input signal to be fuzzified lies. This thus reduces the number of appurtenance functions to be considered, which reduces computing time. The result of the process is a fuzzification of the input signals using the minimum computing time without the need for excessively large storage space of the appurtenance functions.
摘要翻译：模糊处理器包括从输入隶属函数的输入数字信号采取隶属函数值计算模糊化。为此，隶属函数必须保存。为了减少所需的，特别是在高分辨率的输入信号的存储空间，这是方便的由形状决定的功能，例如作为支撑点和斜坡和存储它来描述隶属函数。为了节省计算时间，该Difinitionsbereich输入信号现在分成相等大小的段。在模糊化仅该段被认为是其中信号是fuzzifizierende输入。这增加了考虑隶属函数的数量，从而缩短了处理时间减少。该过程的结果是用最少的计算时间的输入信号的没有存储隶属函数所需的存储器中的模糊化太大。

7. 发明申请

WO1995022099A1 ARRANGEMENT FOR SEPARATELY PROCESSING FUZZY RULES OF DIFFERING IMMPORTANCE 审中-公开
标题翻译： ANRODNUNG与UNTERSCHIELDLICHER重要性模糊规则单独处理
公开(公告)号：WO1995022099A1
公开(公告)日：1995-08-17
申请号：PCT/DE1995000115
申请日：1995-01-25
申请人： SIEMENS AKTIENGESELLSCHAFT , EICHFELD, Herbert , KÜNEMUND, Thomas
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/00
CPC分类号： G06N7/04 , Y10S706/90
摘要： The subject of the application concerns an arrangement in which important (dominant) and less important rules can be stored in a knowledge base store (KBM) separably from one another, in which a new aggregated rule weighting (Gi) is formed from a rule weighting (gi) and an aggregated rule weighting (Gi-1) with an unsharp OR-link and in which the unsharp OR-link is in a unit (BSUM) for forming a limited sum if there is an important rule and in a unit (MAX) for forming a maximum if there is a rule of lesser importance. This ensures that each important rule for which the rule evaluation gives a rule weighting greater than zero affects the sharp value of the initial variables concerned.
摘要翻译：本申请的主题涉及在其中，在一个知识库存储器（KBM）是重要（显性）和规则被存储彼此区分，不那么重要的布置，其中，从一个规则加权（GI），并从一个聚合规则加权（G I-1）与模糊OR 联动，一个新的聚合规则加权（G i）中形成，并且在其中形成一个有限的总和钝化OR联系在一个单元（BSUM）是，如果一个重要的规则是本，和（MAX）是一个单元，用于形成最大值为一个不太重要的规则仍然存在。这确保了每一个重要的规则，所述规则评估为一个控制重量大于零，影响相应的输出变量的急剧值。

8. 发明申请

WO1993005470A1 DIGITAL LOGIC CIRCUIT FOR THE PRODUCTION OF FUZZY-LOGIC OPERATORS 审中-公开
标题翻译：用于生产FUZYY-LOGIC操作器的数字逻辑电路
公开(公告)号：WO1993005470A1
公开(公告)日：1993-03-18
申请号：PCT/DE1992000542
申请日：1992-06-30
申请人： SIEMENS AKTIENGESELLSCHAFT , EICHFELD, Herbert
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/544
CPC分类号： G06F9/30021 , G06F7/544 , G06F2207/3876 , G06N7/04 , Y10S706/90
摘要： The invention concerns a multi-stage digital logic circuit in which for instance a minimum of two input words (A0...A3, B0...B3) are allocated to an output word (C0...C3) and in which output bits (e.g. C3) with a high place value are formed earlier than output bits (e.g. C2, C1 or C0) with a lower place value.

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