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1. 发明授权

US08034670B2 Reliable memory cell 有权
标题翻译：可靠的记忆体
公开(公告)号：US08034670B2
公开(公告)日：2011-10-11
申请号：US12401622
申请日：2009-03-11
申请人： Timothy Phua , Bangun Indajang , Dong Kyun Sohn
发明人： Timothy Phua , Bangun Indajang , Dong Kyun Sohn
IPC分类号： H01L21/335 , H01L29/76
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/66825
摘要： A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner.
摘要翻译：提出了一种形成半导体器件的方法。提供了用第二栅极制备的衬底。处理第二栅极以形成具有圆角的第二栅极，并且在基板上形成第一栅极。第一门与第二门和圆角的一部分相邻并重叠。

2. 发明授权

US07338886B2 Implantation-less approach to fabricating strained semiconductor on isolation wafers 有权
标题翻译：无离子方法在隔离晶圆上制造应变半导体
公开(公告)号：US07338886B2
公开(公告)日：2008-03-04
申请号：US11107712
申请日：2005-04-15
申请人： Jinping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jinping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02395 , H01L21/02447 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/76262 , H01L29/78 , Y10S438/933
摘要： A method of fabricating a semiconductor substrate includes forming a buffer layer on the substrate. A Ge containing layer, such as a SiGe is formed over the buffer layer. The buffer layer includes defects at the interface of the substrate and buffer layer. The substrate is oxidized to transform the buffer layer to a buried oxide layer.
摘要翻译：制造半导体衬底的方法包括在衬底上形成缓冲层。在缓冲层之上形成Ge含Ge层，例如SiGe。缓冲层包括在衬底和缓冲层的界面处的缺陷。将衬底氧化以将缓冲层转变成掩埋氧化物层。

3. 发明申请

US20080014707A1 Process integration scheme of SONOS technology 有权
标题翻译： SONOS技术的过程集成方案
公开(公告)号：US20080014707A1
公开(公告)日：2008-01-17
申请号：US11485949
申请日：2006-07-12
申请人： Sung Mun Jung , Yoke Leng Louis Lim , Sripad Nagarad , Dong Kyun Sohn , Dong Hua Liu , Xiao Yu Chen , Rachel Low
发明人： Sung Mun Jung , Yoke Leng Louis Lim , Sripad Nagarad , Dong Kyun Sohn , Dong Hua Liu , Xiao Yu Chen , Rachel Low
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.
摘要翻译：在非限制性实例中，我们提供具有细胞区域和非细胞区域的底物。我们在衬底上形成隧道介电层，电荷存储层，顶部绝缘层（例如ONO）。然后我们在顶部绝缘层上形成导电焊盘层。我们在焊盘层，电荷存储层和隧道电介质层中形成隔离沟槽并进入衬底。我们在隔离沟中形成隔离区。我们去除非单元区域中的焊盘层，电荷存储层和隧道介电层。我们在衬垫层和衬底表面上形成栅极层。我们完成以形成单元区域中的存储器（例如SONOS）器件和衬底的非单元区域中的其他器件。

4. 发明授权

US07202140B1 Method to fabricate Ge and Si devices together for performance enhancement 有权
标题翻译：将Ge和Si器件制造在一起以提高性能的方法
公开(公告)号：US07202140B1
公开(公告)日：2007-04-10
申请号：US11297540
申请日：2005-12-07
申请人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
发明人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/30
CPC分类号： H01L27/0688 , H01L21/76256 , H01L21/8221 , H01L21/823807 , H01L2924/00011 , H01L2224/80001
摘要： A method for forming a semiconductor structure having devices formed on both sides. A first substrate and a second substrate are provided. The first substrate is preferably comprised of Ge. The second substrate is preferably comprised of silicon. We form a first dielectric layer over the first substrate. We form a first insulating layer over the second substrate. We bond the first dielectric layer and the first dielectric layer to form a first structure. The first structure comprised of the first substrate, an insulation layer (combined first dielectric and first insulating layers) and the second substrate. We reduce the thickness of the first substrate. We form via plugs through the first substrate and the insulation layer and at least partially through the second substrate. We form first active devices on the surface of the first substrate. We form a first capping layer over the first active devices and the first substrate. We reduce the thickness of the second substrate to expose the via plugs. We form second active devices on the second substrate.
摘要翻译：一种用于形成具有形成在两侧的器件的半导体结构的方法。提供第一基板和第二基板。第一衬底优选由Ge组成。第二衬底优选由硅组成。我们在第一衬底上形成第一电介质层。我们在第二衬底上形成第一绝缘层。我们键合第一介电层和第一介电层以形成第一结构。第一结构包括第一基底，绝缘层（组合的第一介电层和第一绝缘层）和第二基底。我们减少第一个基板的厚度。我们通过插塞穿过第一基底和绝缘层形成，并且至少部分地穿过第二基底。我们在第一衬底的表面上形成第一有源器件。我们在第一有源器件和第一衬底上形成第一覆盖层。我们减小第二基板的厚度以露出通孔塞。我们在第二个基板上形成第二个有源器件。

5. 发明授权

US06995078B2 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US06995078B2
公开(公告)日：2006-02-07
申请号：US10763305
申请日：2004-01-23
申请人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses. In situ growth of an overlying silicon—germanium layer featuring uniform or non—graded germanium content, results in a relaxed silicon—germanium layer with a minimum of dislocations propagating from the underlying graded silicon—germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

6. 发明授权

US06251780B1 Method for fabricating thin film at high temperature 有权
标题翻译：在高温下制造薄膜的方法
公开(公告)号：US06251780B1
公开(公告)日：2001-06-26
申请号：US09524394
申请日：2000-03-13
申请人： Dong Kyun Sohn , Ji Soo Park , Jong Uk Bae
发明人： Dong Kyun Sohn , Ji Soo Park , Jong Uk Bae
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： A method for fabricating a semiconductor device includes the steps of forming a refractory metal film on a semiconductor substrate, forming a capping film on the refractory metal film, injecting IV group atoms into the capping film to knock atoms of the capping film into the refractory metal film, and forming a metal silicide film at an interface between the semiconductor substrate and the refractory metal film.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成难熔金属膜，在难熔金属膜上形成封盖膜，将IV族原子注入封盖膜中，将封盖膜的原子敲入难熔金属并且在半导体衬底和难熔金属膜之间的界面处形成金属硅化物膜。

7. 发明授权

US08358007B2 Integrated circuit system employing low-k dielectrics and method of manufacture thereof 有权
标题翻译：采用低k电介质的集成电路系统及其制造方法
公开(公告)号：US08358007B2
公开(公告)日：2013-01-22
申请号：US12796610
申请日：2010-06-08
申请人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
发明人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/3105 , H01L21/31155 , H01L21/76825 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76859 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.
摘要翻译：集成电路系统的制造方法包括：制造具有集成电路的基板; 在集成电路上施加低K电介质层; 在低K电介质层中形成通孔和沟槽，在集成电路上; 通过化学机械平面化（CMP）工艺形成结构表面; 以及对由CMP工艺引起的用于形成植入层和金属钝化层的直接植入物施加到包括修复损伤的低K电介质层。

8. 发明申请

US20100001370A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS 有权
标题翻译：集成电路系统采用替代导电层
公开(公告)号：US20100001370A1
公开(公告)日：2010-01-07
申请号：US12168816
申请日：2008-07-07
申请人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
发明人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
IPC分类号： H01L21/768 , H01L21/02 , H01L27/06
CPC分类号： H01L23/5223 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
摘要翻译：一种集成电路系统，包括：提供包括前端电路的基板; 形成包括在所述衬底上的第一导电迹线的第一导电电平; 形成与所述第一导电电平间隔开并包括第二导电迹线的第二导电电平; 以及将第一导电电平与通过第二导电电平而不接触第二导电迹线的viabar连接到第三导电电平。

9. 发明申请

US20080032513A1 INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY 有权
标题翻译：集成电路系统，包括氮化层技术
公开(公告)号：US20080032513A1
公开(公告)日：2008-02-07
申请号：US11428618
申请日：2006-07-05
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种集成电路系统，包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

10. 发明授权

US07166522B2 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US07166522B2
公开(公告)日：2007-01-23
申请号：US10865433
申请日：2004-06-10
申请人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054
摘要： A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent, overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses. In situ growth of an overlying silicon-germanium layer featuring uniform or non-graded germanium content, results in a relaxed silicon-germanium layer with a minimum of dislocations propagating from the underlying graded silicon-germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

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