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    • 5. 发明授权
    • Data processing system with apparatus for correcting microinstruction
errors
    • 具有用于校正微指令误差的装置的数据处理系统
    • US4231089A
    • 1980-10-28
    • US969956
    • 1978-12-15
    • Donald A. LewineThomas M. DundonRonald J. Setera
    • Donald A. LewineThomas M. DundonRonald J. Setera
    • G06F11/10G06F11/14G06F11/16
    • G06F11/1008G06F11/1076G06F11/141
    • In a data processing system, a method and apparatus which enable an erroneous microinstruction word to be rewritten before it is executed. After the microinstruction word is written from memory into a control register, a parity network coupled to the control register determines whether a correct microinstruction is being executed. Upon a parity error being detected, the clock pulses to the data paths coupled to the control register are inhibited. The original microinstruction word is then fetched from secondary storage and rewritten into the microinstruction memory with the aid of a separate register providing the address to the microinstruction memory. Upon rewriting the microinstruction memory, the signal inhibiting the clock pulses is removed thereby allowing a new microinstruction to be executed. An additional feature includes apparatus for determining whether an error has previously occurred for the same microinstruction word, in which case a critical fault occurs and remedial maintenance is necessary.
    • 在数据处理系统中,能够在执行错误的微指令词之前重写该方法和装置。 在微指令字从存储器写入控制寄存器之后,耦合到控制寄存器的奇偶校验网络确定是否正在执行正确的微指令。 在检测到奇偶校验错误时,禁止连接到控制寄存器的数据通路的时钟脉冲。 然后从辅助存储器取出原始微指令字,借助于向微指令存储器提供地址的单独寄存器将其重新写入微指令存储器。 在重写微指令存储器时,消除了抑制时钟脉冲的信号,从而允许执行新的微指令。 附加特征包括用于确定是否先前针对相同的微指令词发生错误的装置,在这种情况下发生严重故障并且需要补救维护。
    • 6. 发明授权
    • Parity processing in arithmetic operations
    • 算术运算中的奇偶校验处理
    • US4224681A
    • 1980-09-23
    • US969955
    • 1978-12-15
    • Donald A. Lewine
    • Donald A. Lewine
    • G06F11/10
    • G06F11/10
    • Method and apparatus for parity checking of data, particularly in relation to data used and/or generated by an arithmetic logic unit of a data processing system. Parity is generated for all operations but examined only in connection with those operations which results in valid parity. For these operations which do not directly result in valid parity, parity is ignored. A "parity valid" bit is associated with those operations which generate valid parity and a parity error is indicated only when the parity valid bit occurs at the same time as a parity error.
    • 数据的奇偶校验方法和装置,特别是与数据处理系统的算术逻辑单元使用和/或产生的数据有关。 产生所有操作的奇偶校验,但仅对导致有效奇偶校验的操作进行检查。 对于不直接导致有效奇偶校验的这些操作,忽略奇偶校验。 “奇偶校验有效”位与产生有效奇偶校验的那些操作相关联,并且仅当奇偶校验有效位与奇偶校验错误同时出现时才指示奇偶校验错误。