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1. 发明授权

US07401134B2 Packet processing architecture 有权
标题翻译：数据包处理架构
公开(公告)号：US07401134B2
公开(公告)日：2008-07-15
申请号：US10523181
申请日：2003-07-25
申请人： Didier Velez , Patrick Lopez , Vincent Demoulin
发明人： Didier Velez , Patrick Lopez , Vincent Demoulin
IPC分类号： G06F15/177 , G06F11/00
CPC分类号： H04L1/0025 , H04L29/06 , H04L49/351 , H04L69/12 , H04L69/18 , H04L69/22
摘要： A system for processing data packets comprising a plurality of data processing blocks and a controller, which allows the configuration parameters used in processing the data blocks to be updated in each data processing blocks at the data packet boundary. The present invention involves a system that utilizes a handshaking method for synchronously exchanging data between data processing blocks, wherein the data processing blocks update configuration parameters based on the type of networking standard used. Each data processing block identifies a first data block in the data packet and transmits a first data signal along with a first output data block of the data packet, wherein the block updates the configuration parameters from the controller only when the first data signal is present. In this manner, the first data signal, which is indicative of the data packet boundary, is propagated along the sequence of data processing blocks.
摘要翻译：一种用于处理数据包的系统，包括多个数据处理块和控制器，其允许在数据分组边界的每个数据处理块中更新用于处理数据块的配置参数。本发明涉及利用握手方法在数据处理块之间同步交换数据的系统，其中数据处理块基于所使用的联网标准的类型来更新配置参数。每个数据处理块识别数据分组中的第一数据块，并且与数据分组的第一输出数据块一起发送第一数据信号，其中，仅当存在第一数据信号时，该块才从控制器更新配置参数。以这种方式，指示数据分组边界的第一数据信号沿着数据处理块的序列被传播。

2. 发明申请

US20060031424A1 Packet signal processing architecture 有权
标题翻译：分组信号处理架构
公开(公告)号：US20060031424A1
公开(公告)日：2006-02-09
申请号：US10523181
申请日：2003-07-25
申请人： Didier Velez , Patrick Lopez , Vincent Demoulin
发明人： Didier Velez , Patrick Lopez , Vincent Demoulin
IPC分类号： G06F15/177
CPC分类号： H04L1/0025 , H04L29/06 , H04L49/351 , H04L69/12 , H04L69/18 , H04L69/22
摘要： A system for processing data packets comprising a plurality of data processing blocks and a controller, which allows the configuration parameters used in processing the data blocks to be updated in each data processing blocks at the data packet boundary. The present invention involves a system that utilizes a handshaking method for synchronously exchanging data between data processing blocks, wherein the data processing blocks update configuration parameters based on the type of networking standard used. Each data processing block identifies a first data block in the data packet and transmits a first data signal along with a first output data block of the data packet, wherein the block updates the configuration parameters from the controller only when the first data signal is present. In this manner, the first data signal, which is indicative of the data packet boundary, is propagated along the sequence of data processing blocks.
摘要翻译：一种用于处理数据包的系统，包括多个数据处理块和控制器，其允许在数据分组边界的每个数据处理块中更新用于处理数据块的配置参数。本发明涉及利用握手方法在数据处理块之间同步交换数据的系统，其中数据处理块基于所使用的联网标准的类型来更新配置参数。每个数据处理块识别数据分组中的第一数据块，并且与数据分组的第一输出数据块一起发送第一数据信号，其中，仅当存在第一数据信号时，该块才从控制器更新配置参数。以这种方式，指示数据分组边界的第一数据信号沿着数据处理块的序列被传播。

3. 发明授权

US06920600B2 Dual chien search blocks in an error-correcting decoder 有权
标题翻译：纠错解码器中的双重搜索块
公开(公告)号：US06920600B2
公开(公告)日：2005-07-19
申请号：US10055076
申请日：2002-01-23
申请人： Louis Robert Litwin, Jr. , Didier Velez
发明人： Louis Robert Litwin, Jr. , Didier Velez
IPC分类号： G06F11/10 , G11B20/18 , H03M13/15 , H04L1/00
CPC分类号： H03M13/1555 , H03M13/15 , H03M13/1545 , H03M13/1585
摘要： A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator, an error polynomial is generated based upon the syndrome in an error polynomial generator, an error location is determined from the error polynomial in the error location generator, an error magnitude is calculated from the error polynomial in the error magnitude generator and the codeword is corrected by a error corrected codeword generator responsive to location and error magnitude. An intra-decoder block messaging scheme is described in which one or more components generate inactivity messages to signal an ability to process data corresponding to a next codeword. A dual Chien search block implementation is described in which Chien block is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block. An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block implemented with a LIFO register.
摘要翻译：描述了一种解码器和解码方法，其中从校正子发生器中的码字计算出校正子，根据误差多项式生成器中的校正子产生误差多项式，根据误差位置中的误差多项式确定误差位置发生器，误差幅度由误差多项式在误差幅度发生器中计算，并且码字由响应于位置和误差幅度的纠错码字发生器校正。描述了解码器内消息传送方案，其中一个或多个组件产生不活动消息以发出处理对应于下一个码字的数据的能力。描述了双Chien搜索块实现，其中Chien块用于确定与指定码字相对应的错误的数量，与由Chien / Forney块执行的错误位置和幅度计算分开。描述了一种增强的Chien搜索单元架构，其利用附加的伽罗瓦域加法器来同步码字和误差向量，从而减少与利用LIFO寄存器实现的纠错块相对应的延迟和费用。

4. 发明授权

US07020826B2 Intra-decoder component block messaging 失效
公开(公告)号：US07020826B2
公开(公告)日：2006-03-28
申请号：US10055114
申请日：2002-01-23
申请人： Louis Robert Litwin, Jr. , Didier Velez
发明人： Louis Robert Litwin, Jr. , Didier Velez
IPC分类号： H03M13/00
CPC分类号： G11B20/1803 , G11B20/10296 , H03M13/1515 , H03M13/1555
摘要： A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator, an error polynomial is generated based upon the syndrome in an error polynomial generator, an error location is determined from the error polynomial in the error location generator, an error magnitude is calculated from the error polynomial in the error magnitude generator and the codeword is corrected by a error corrected codeword generator responsive to location and error magnitude. An intra-decoder block messaging scheme is described in which one or more components generate inactivity messages to signal an ability to process data corresponding to a next codeword. A dual Chien search block implementation is described in which Chien block is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block. An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block implemented with a LIFO register.

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