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1. 发明授权

US5731612A Insulated gate field effect transistor structure having a unilateral source extension 失效
标题翻译：具有单边源延伸的绝缘栅场效应晶体管结构
公开(公告)号：US5731612A
公开(公告)日：1998-03-24
申请号：US842097
申请日：1997-04-28
申请人： Juan Buxo , Diann Dow , Vida Ilderem , Ziye Zhou , Thomas E. Zirkle
发明人： Juan Buxo , Diann Dow , Vida Ilderem , Ziye Zhou , Thomas E. Zirkle
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66659 , H01L29/1083
摘要： An insulated gate field effect transistor (IGFET) structure (10) includes a source region (14) and a drain region (16) formed in an impurity well (13). A channel region (18) separates the source region (14) from the drain region (16). In one embodiment, a unilateral extension region (17) is formed adjacent the source region (14) only and extends into the channel region (18). The unilateral extension region (17) has a peak dopant concentration at a depth (23) and a lateral distance (24) to provide punchthrough resistance. The IGFET structure (10) is suitable for low (i.e., 0.2-0.3 volts) to medium (0.5-0.6 volts) threshold voltage reduced channel length applications.
摘要翻译：绝缘栅场效应晶体管（IGFET）结构（10）包括形成在杂质阱（13）中的源区（14）和漏区（16）。沟道区域（18）将源极区域（14）与漏极区域（16）分离。在一个实施例中，单侧延伸区域（17）仅形成在邻近源极区域（14）处并延伸到沟道区域（18）中。单侧延伸区域（17）在深度（23）和横向距离（24）处具有峰值掺杂剂浓度以提供穿透阻力。 IGFET结构（10）适用于低（即0.2-0.3伏特）至中等（0.5-0.6伏）阈值电压降低的信道长度应用。

2. 发明授权

US5675166A FET with stable threshold voltage and method of manufacturing the same 失效
标题翻译：具有稳定阈值电压的FET及其制造方法
公开(公告)号：US5675166A
公开(公告)日：1997-10-07
申请号：US499624
申请日：1995-07-07
申请人： Vida Ilderem , Michael H. Kaneshiro , Diann Dow
发明人： Vida Ilderem , Michael H. Kaneshiro , Diann Dow
IPC分类号： H01L29/78 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L29/0847 , H01L29/1045 , H01L29/665 , H01L29/6656 , H01L29/66659
摘要： A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.
摘要翻译：低电压场效应晶体管结构（20）被提供有允许改变源植入区域（41）的位置的工艺变化的阈值电压。形成与源区（41）相邻的第一晕区（33）和第二晕区（36），使得在随后的热处理之后，在通道区域（41）中形成具有与源区（41）相反的导电性的恒定掺杂分布（23），邻近源极区域（41）。实施例可以形成为仅与源极区域（41）相邻以产生单侧器件，或者可以在源极区域（41）和漏极区域（40）附近形成掺杂分布以产生双边器件。另外的实施例在源区（41）中形成第二注入区以减少结漏电流。

3. 发明授权

US5541132A Insulated gate semiconductor device and method of manufacture 失效
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：US5541132A
公开(公告)日：1996-07-30
申请号：US408653
申请日：1995-03-21
申请人： Robert B. Davies , Vida Ilderem , Mark D. Griswold , Diann Dow , James E. Prendergast , Iksung Lim , Juan Buxo , Richard D. Sivan , James D. Burnett , Frank K. Baker
发明人： Robert B. Davies , Vida Ilderem , Mark D. Griswold , Diann Dow , James E. Prendergast , Iksung Lim , Juan Buxo , Richard D. Sivan , James D. Burnett , Frank K. Baker
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/423 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/823814 , H01L21/823828 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/1045 , H01L29/1083 , H01L29/42368 , Y10S438/981
摘要： An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).
摘要翻译：具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。掺杂剂阱（13）形成在半导体材料（11）中。栅极氧化物层（26）形成在掺杂剂阱（13）上，其中栅极氧化物层（26）和具有栅极接触部分（43）和栅极延伸部分（44）的栅极结构（41）。栅极接触部分（43）允许与栅极结构（41）的电接触，而栅极延伸部分（44）用作有源栅极部分。与栅极接触部分（43）相邻的栅极氧化物（26）的一部分被加厚以降低场效应晶体管（10）的栅极到漏极电容，从而增加绝缘栅极场效应晶体管（10）的带宽。

4. 发明授权

US5482878A Method for fabricating insulated gate field effect transistor having subthreshold swing 失效
标题翻译：具有亚阈值摆幅的绝缘栅场效应晶体管的制造方法
公开(公告)号：US5482878A
公开(公告)日：1996-01-09
申请号：US223393
申请日：1994-04-04
申请人： Vida I. Burger , Michael H. Kaneshiro , Diann Dow , Kevin M. Klein , Michael P. Masquelier , E. James Prendergast
发明人： Vida I. Burger , Michael H. Kaneshiro , Diann Dow , Kevin M. Klein , Michael P. Masquelier , E. James Prendergast
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/265
CPC分类号： H01L27/0928 , H01L21/823807 , H01L29/7835
摘要： Insulated gate field effect transistors (10, 70) having process steps for setting the V.sub.T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V.sub.T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V.sub.T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.
摘要翻译：绝缘栅场效应晶体管（10,70）具有用于设置VT和器件漏电流的工艺步骤，所述工艺步骤与用于提供穿透保护的工艺步骤分离，从而降低亚阈值摆幅。在单侧晶体管（10）中，源极区（48,51）和漏极区（49,52）之间的掺杂剂层（25,30）的部分（37,45）用作沟道区域，并将 VT和器件漏电流。光晕区域（34,39）包含源极区域（48,51）并设置穿透电压。在双向晶体管（70）中，源极区域（83,86）和漏极区域（84,87）都包含在光晕区域（75,74,79,81）内。掺杂剂层（25,30）的一部分（76,82）设定VT和漏电流，而光晕区域（75,79）设定穿透电压。

5. 发明授权

US6017798A FET with stable threshold voltage and method of manufacturing the same 失效
标题翻译：具有稳定阈值电压的FET及其制造方法
公开(公告)号：US6017798A
公开(公告)日：2000-01-25
申请号：US865846
申请日：1997-06-02
申请人： Vida Ilderem , Michael H. Kaneshiro , Diann Dow
发明人： Vida Ilderem , Michael H. Kaneshiro , Diann Dow
IPC分类号： H01L29/78 , H01L21/336 , H01L29/08 , H01L29/10
CPC分类号： H01L29/6659 , H01L29/0847 , H01L29/1045 , H01L29/665 , H01L29/6656 , H01L29/66659
摘要： A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.
摘要翻译：低电压场效应晶体管结构（20）被提供有允许改变源植入区域（41）的位置的工艺变化的阈值电压。形成与源区（41）相邻的第一晕区（33）和第二晕区（36），使得在随后的热处理之后，在通道区域（41）中形成具有与源区（41）相反的导电性的恒定掺杂分布（23），邻近源极区域（41）。实施例可以形成为仅与源极区域（41）相邻以产生单侧器件，或者可以在源极区域（41）和漏极区域（40）附近形成掺杂分布以产生双边器件。另外的实施例在源区（41）中形成第二注入区以减少结漏电流。

6. 发明授权

US5427964A Insulated gate field effect transistor and method for fabricating 失效
标题翻译：绝缘栅场效应晶体管及其制造方法
公开(公告)号：US5427964A
公开(公告)日：1995-06-27
申请号：US223394
申请日：1994-04-04
申请人： Michael H. Kaneshiro , Diann Dow
发明人： Michael H. Kaneshiro , Diann Dow
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/823807
摘要： Insulated gate field effect transistors (10, 70) having independent process steps for setting lateral and vertical dopant profiles for source and drain regions. In a unilateral transistor (10) , portions (48, 50, 51, 55) of the source region are contained within a halo region (34, 41) whereas portions (49, 47, 52, 64) of the drain region are non contained within a halo region. The source region (60, 65) has a first portion (48, 51) for setting a channel length and a second portion (50, 55 ) for setting a breakdown voltage and a source/drain capacitance. The second portion (50, 55) extends further into the halo region than the first portion (48, 51). In a bilateral transistor (70), portions (84, 89, 90, 91) of the drain region (72, 87) are contained within halo region (75, 79 ).
摘要翻译：绝缘栅场效应晶体管（10,70）具有用于设置源极和漏极区域的横向和垂直掺杂物分布的独立工艺步骤。在单侧晶体管（10）中，源极区域的部分（48,50,51,55）包含在卤素区域（34,41）内，而漏极区域的部分（49,47,52,64）不是包含在光晕区域内。源区域（60,65）具有用于设定沟道长度的第一部分（48,51）和用于设置击穿电压和源极/漏极电容的第二部分（50,55）。第二部分（50,55）比第一部分（48,51）进一步延伸到晕圈区域。在双向晶体管（70）中，漏极区域（72,87）的部分（84,89,90,91）包含在光晕区域（75,79）内。

7. 发明申请

US20060246652A1 Method of forming a semiconductor device and structure therefor 有权
公开(公告)号：US20060246652A1
公开(公告)日：2006-11-02
申请号：US11119106
申请日：2005-05-02
申请人： Gordon Grivna , Peter Zdebel , Diann Dow
发明人： Gordon Grivna , Peter Zdebel , Diann Dow
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0635 , H01L27/0676
摘要： A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die.

8. 发明申请

US20050145945A1 High energy ESD structure and method 有权
标题翻译：高能ESD结构及方法
公开(公告)号：US20050145945A1
公开(公告)日：2005-07-07
申请号：US10750267
申请日：2004-01-02
申请人： Peter Zdebel , Diann Dow
发明人： Peter Zdebel , Diann Dow
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0255
摘要： In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.
摘要翻译：在一个实施例中，同心环ESD结构包括第一p型区域和第二p型区域形成在半导体材料层中。两个p型区域与浮动n型掩埋层耦合在一起。第一和第二p型区域形成具有浮置n型掩埋层的背对背二极管结构。在第一和第二区域的每一个中形成一对短路的n型和p型接触区域。在第一和第二p型区域之间形成隔离区域。

9. 发明授权

US07638385B2 Method of forming a semiconductor device and structure therefor 有权
标题翻译：形成半导体器件的方法及其结构
公开(公告)号：US07638385B2
公开(公告)日：2009-12-29
申请号：US11119106
申请日：2005-05-02
申请人： Gordon M. Grivna , Peter J. Zdebel , Diann Dow
发明人： Gordon M. Grivna , Peter J. Zdebel , Diann Dow
IPC分类号： H01L21/8238 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0635 , H01L27/0676
摘要： A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die.
摘要翻译：形成半导体器件的方法包括形成隔离沟槽，用于将半导体管芯上的诸如晶体管，二极管，电容器或电阻器的电气元件中的一些电元件与半导体管芯上的其它元件隔离。

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