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1. 发明申请

US20070201281A1 DECODING TECHNIQUES FOR READ-ONLY MEMORY 有权
标题翻译：解读只读存储器的技术
公开(公告)号：US20070201281A1
公开(公告)日：2007-08-30
申请号：US11363366
申请日：2006-02-27
申请人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
发明人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
IPC分类号： G11C7/00 , G11C8/00 , G11C7/10
CPC分类号： H01L27/112 , G11C7/12 , G11C7/18 , G11C17/10 , H01L27/0207
摘要： A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic units are also provided, corresponding to the bit line structures. Each of the column sense logic units includes a first logic gate and a second logic gate. The first logic gate has a first input connected with a first one of the bit lines and a second input connected with a second one of the bit lines. The second logic gate has a first input interconnected with a third one of the bit lines, and a second input interconnected with the second one of the bit lines.
摘要翻译：存储器电路包括多个位线结构，每个位线结构包括至少三个位线; 在多个位置处与位线结构相交的许多字线; 以及位于这些站点的多个交换设备。还提供了多个列读出逻辑单元，对应于位线结构。每个列感知逻辑单元包括第一逻辑门和第二逻辑门。第一逻辑门具有与第一位线连接的第一输入端和与第二位线连接的第二输入端。第二逻辑门具有与位线中的第三位相互连接的第一输入，以及与第二位线互连的第二输入。

2. 发明申请

US20100046291A1 Process and Temperature Tolerant Non-Volatile Memory 有权
标题翻译：过程和耐温非挥发性记忆
公开(公告)号：US20100046291A1
公开(公告)日：2010-02-25
申请号：US12194028
申请日：2008-08-19
申请人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
发明人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C7/062 , G11C7/02 , G11C7/04 , G11C17/16 , G11C17/18
摘要： A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.
摘要翻译：一种包括存储器单元阵列和读出放大器的非易失性存储器，每个读出放大器使用保持器电路来提供一定量的电流来补偿存储器阵列中的位线泄漏电流。保持器的电流量取决于存储器的温度和用于制作存储器的处理速度。

3. 发明授权

US07755948B2 Process and temperature tolerant non-volatile memory 有权
标题翻译：过程和耐温非易失性存储器
公开(公告)号：US07755948B2
公开(公告)日：2010-07-13
申请号：US12194028
申请日：2008-08-19
申请人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
发明人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
IPC分类号： G11C16/06
CPC分类号： G11C7/062 , G11C7/02 , G11C7/04 , G11C17/16 , G11C17/18
摘要： A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.
摘要翻译：一种包括存储器单元阵列和读出放大器的非易失性存储器，每个读出放大器使用保持器电路来提供一定量的电流来补偿存储器阵列中的位线泄漏电流。保持器的电流量取决于存储器的温度和用于制作存储器的处理速度。

4. 发明申请

US20070201257A1 Layout techniques for read-only memory and the like 有权
标题翻译：只读存储器的布局技术等
公开(公告)号：US20070201257A1
公开(公告)日：2007-08-30
申请号：US11363010
申请日：2006-02-27
申请人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
发明人： Dennis Dudeck , Donald Evans , Hai Pham , Wayne Werner , Ronald Wozniak
IPC分类号： G11C5/06 , G11C17/00
CPC分类号： G11C5/063 , G11C17/10 , H01L27/0207 , H01L27/112
摘要： An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of VSS planes are interconnected with the switching devices. The switching devices and the VSS planes are formed at a first level. The VSS planes can be formed as substantially complementary interlocking regions that also form functional portions of the switching devices. The switching devices can be connected between an adjacent one of the word lines and a selected one of the bit lines of an adjacent one of the bit line structures for selective electrical conduction therebetween upon activation by the adjacent one of the word lines.
摘要翻译：集成电路包括具有多个位线结构的存储器电路，每个包括至少三个位线; 在多个位置处与位线结构相交的许多字线; 以及位于这些站点的多个交换设备。一些V SS平面与开关装置互连。开关装置和V SS平面形成在第一级。 V SS平面可以形成为也形成开关装置的功能部分的基本上互补的互锁区域。开关器件可以连接在相邻的一个字线和位线结构中相邻的一个位线结构中的所选位线之间，以便在相邻的一个字线激活之后选择性地导电。

5. 发明申请

US20070103953A1 CONTENT ADDRESSABLE MEMORIES (CAMs) BASED ON A BINARY CAM AND HAVING AT LEAST THREE STATES 有权
标题翻译：内容可寻址记忆（CAM）基于二进制CAM并且具有至少三个状态
公开(公告)号：US20070103953A1
公开(公告)日：2007-05-10
申请号：US11619889
申请日：2007-01-04
申请人： Duane Aadsen , Dennis Dudeck , Donald Evans
发明人： Duane Aadsen , Dennis Dudeck , Donald Evans
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bits as a single CAM bit having said at least three states. The three states include a don't care state, a logic 0 state and a logic 1 state. The logic circuit may be embodied as two OR gates. The first match search (MS) input and a first wild card (WC) input of the higher order CAM are applied to inputs of the two OR gates and the outputs of the two OR gates are applied to the wild card (WC) inputs of the binary CAM. The match search (MS) inputs of the binary CAM are tied to a power supply voltage.
摘要翻译：公开了提供至少三种状态并且基于现有的二进制CAM设备的内容可寻址存储器。具有至少三个状态的高阶CAM包括具有两个二进制位的二进制CAM; 以及将所述两个二进制位配置为具有所述至少三个状态的单个CAM位的逻辑电路。这三个状态包括无关状态，逻辑0状态和逻辑1状态。逻辑电路可以被实现为两个OR门。将高阶CAM的第一匹配搜索（MS）输入和第一通配符（WC）输入应用于两个或门的输入，并且两个或门的输出被施加到通配符（WC）输入的通配符二进制CAM。二进制CAM的匹配搜索（MS）输入与电源电压相关。

6. 发明申请

US20110222357A1 Process and Temperature Tolerant Non-Volatile Memory 有权
标题翻译：过程和耐温非挥发性记忆
公开(公告)号：US20110222357A1
公开(公告)日：2011-09-15
申请号：US12756401
申请日：2010-04-08
申请人： Dennis Dudeck , Donald Evans , Hai Pham , Ronald Wozniak , Wayne Werner
发明人： Dennis Dudeck , Donald Evans , Hai Pham , Ronald Wozniak , Wayne Werner
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/04 , G11C17/16 , G11C17/18
摘要： A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.
摘要翻译：一种包括存储器单元阵列和读出放大器的非易失性存储器，每个读出放大器使用保持器电路来提供一定量的电流来补偿存储器阵列中的位线泄漏电流。保持器的电流量取决于存储器的温度和用于制作存储器的处理速度。

7. 发明申请

US20050162952A1 Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays 有权
标题翻译：用于使用预充电子阵列在只读存储器件中减少泄漏电流的方法和装置
公开(公告)号：US20050162952A1
公开(公告)日：2005-07-28
申请号：US10764152
申请日：2004-01-23
申请人： Dennis Dudeck , Donald Evans , Richard McPartland , Hai Quang Pham
发明人： Dennis Dudeck , Donald Evans , Richard McPartland , Hai Quang Pham
IPC分类号： G11C7/12 , G11C17/12 , G11C7/00
CPC分类号： G11C17/12 , G11C7/12
摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.
摘要翻译：提供了一种用于减少只读存储器件中的漏电流的方法和装置。在给定的读取周期期间，通过在只读存储器阵列中只预先充电一部分列来减少泄漏电流。预充电的列的部分被限制为包括在给定读周期期间将被读取的列的列的子集。对读取列地址进行解码，以仅对在给定读取周期期间将被读取的晶体管列的部分进行预充电。晶体管的列可以被分组成多个子阵列，并且仅在具有在给定读周期期间被读取的列的那些子阵列在读周期期间被预充电。

8. 发明授权

US08059472B2 Process and temperature tolerant non-volatile memory 有权
标题翻译：过程和耐温非易失性存储器
公开(公告)号：US08059472B2
公开(公告)日：2011-11-15
申请号：US12756401
申请日：2010-04-08
申请人： Dennis Dudeck , Donald Evans , Hai Pham , Ronald Wozniak , Wayne Werner
发明人： Dennis Dudeck , Donald Evans , Hai Pham , Ronald Wozniak , Wayne Werner
IPC分类号： G11C11/34
CPC分类号： G11C7/062 , G11C7/02 , G11C7/04 , G11C17/16 , G11C17/18
摘要： A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.
摘要翻译：一种包括存储器单元阵列和读出放大器的非易失性存储器，每个读出放大器使用保持器电路来提供一定量的电流来补偿存储器阵列中的位线泄漏电流。保持器的电流量取决于存储器的温度和用于制作存储器的处理速度。

9. 发明申请

US20070103959A1 Method And Apparatus For Reducing Leakage Current In A Read Only Memory Device Using Shortened Precharge Phase 有权
标题翻译：用于减少预充电相位的只读存储器件中的泄漏电流的方法和装置
公开(公告)号：US20070103959A1
公开(公告)日：2007-05-10
申请号：US11619344
申请日：2007-01-03
申请人： Dennis Dudeck , Donald Evans , Richard McPartland , Hai Pham
发明人： Dennis Dudeck , Donald Evans , Richard McPartland , Hai Pham
IPC分类号： G11C17/00
CPC分类号： G11C7/12 , G11C17/12
摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced
摘要翻译：提供了一种用于减少只读存储器件中的漏电流的方法和装置。通过在每个读取周期期间减少预充电周期的持续时间来降低泄漏电流，使得相关联的泄漏电流将在每个周期期间流动更短的时间段。预充电阶段位于每个读取周期的开始之前，在评估阶段之前。预充电阶段由后续时钟边沿或后续时钟边沿之前的内部超时终止。列达到其预充电电压和评估阶段开始的时间间隔减小

10. 发明申请

US20050162951A1 Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase 有权
标题翻译：使用缩短的预充电阶段来减少只读存储器件中的泄漏电流的方法和装置
公开(公告)号：US20050162951A1
公开(公告)日：2005-07-28
申请号：US10764150
申请日：2004-01-23
申请人： Dennis Dudeck , Donald Evans , Richard McPartland , Hai Pham
发明人： Dennis Dudeck , Donald Evans , Richard McPartland , Hai Pham
IPC分类号： G11C7/00 , G11C7/12 , G11C17/12
CPC分类号： G11C7/12 , G11C17/12
摘要： A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.
摘要翻译：提供了一种用于减少只读存储器件中的漏电流的方法和装置。通过在每个读取周期期间减少预充电周期的持续时间来降低泄漏电流，使得相关联的泄漏电流将在每个周期期间流动更短的时间段。预充电阶段位于每个读取周期的开始之前，在评估阶段之前。预充电阶段由后续时钟边沿或后续时钟边沿之前的内部超时终止。列达到其预充电电压和评估阶段开始之间的时间间隔减小。

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