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1. 发明授权

US4005387A Computer control system 失效
公开(公告)号：US4005387A
公开(公告)日：1977-01-25
申请号：US643350
申请日：1975-12-22
申请人： William M. Herring , Dennis B. Walling
发明人： William M. Herring , Dennis B. Walling
IPC分类号： G06F3/00 , G06F15/46
CPC分类号： G05B19/04
摘要： During the use of process equipment it is necessary to position control valves, change analog set-point signals for process controllers, move thermocouples to specific positions in thermowells, etc. A computer control system for these operations utilizes binary information on three sets of bits of a bus and an execute signal on another bit provided by a computer, usually at a remote area, to select the device of the equipment to be changed and to make the change. The system includes: an information interface card; a number of actuator module cards; decoder/demultiplexer means; and device select means. The interface card is connectable to first and second sets of bits of a bus that is connectable to additional systems. The device select means is connected to a third set of bits of the bus. The binary information to the device select means results in a signal only at one of its outputs, each output being connected to a different system. For the computer control system that output is connected to the input of first inverter means on the interface card. Second inverter means on the interface card is connectable to that another bit of the bus to receive the execute pulse to initiate the operation of the system, if selected by the device selector means. First and second gate means on the card have for each a number of gates with first and second inputs and an output. Means connected to these first inputs of the first and second gate means are connectable to different bits of the first and second sets, respectively, of bits of the bus. The second inputs of the first and second gate means are connected to the output of the first inverter means to open the gates when that inverter means is provided the device select signal. The inputs of the decoder/demultiplexer are connected to the outputs of the gates of the second gate means. Each actuator module card includes: storage buffer means having inputs corresponding in number to the number of gates of the first gate means, a corresponding number of outputs, and an additional input to receive a load signal to provide at those outputs retained binary information corresponding to the signals at the outputs of the gates of the first gate means at the completion of the load signal; means responsive to binary information at the outputs of the storage buffer means to provide at least one signal to change the operation of a device of the process equipment; a gate; and additional inverter means having an input and having its output connected to an input of the gate, while the output of the gate is connected to the load input of the storage buffer means. Another input of that gate on each module card is connected to the output of the second inverter means on the interface card to provide a load signal to the storage buffer means, when the additional inverter means of that card is signalled by the decoder/demultiplexer means to signal the means to change the device of the process equipment. The additional inverter means have their inputs connected to different outputs of the decoder/demultiplexer means.

2. 发明授权

US3968487A Multiplexer-analog/digital conversion system 失效
标题翻译：多路复用器模拟/数字转换系统
公开(公告)号：US3968487A
公开(公告)日：1976-07-06
申请号：US514495
申请日：1974-10-15
申请人： William M. Herring , Dennis B. Walling
发明人： William M. Herring , Dennis B. Walling
IPC分类号： G06F17/40 , G06F3/00
CPC分类号： H03M1/1225 , H04L25/0272
摘要： The system includes: a number of subassemblies, each containing a set of switches connectable at their pair of inputs to different sources of analog signals and containing a multiplexer/decoder having outputs connected to different switches for their selective actuation; a differential amplifier having a pair of inputs connected to the pair of outputs of all of the switches; analog/digital converter means having its input connected to the output of the amplifier and having outputs providing multi-bit digital information; and control means that provides various functions.
摘要翻译：该系统包括：多个子组件，每个子组件包含一组可在其输入对上连接到不同的模拟信号源的开关，并且包含具有连接到不同开关的输出以用于其选择性致动的多路复用器/解码器; 差分放大器，其具有连接到所有开关的所述一对输出的一对输入; 模拟/数字转换器意味着其输入连接到放大器的输出并且具有提供多位数字信息的输出; 以及提供各种功能的控制装置。

3. 发明授权

US4024501A Line driver system 失效
公开(公告)号：US4024501A
公开(公告)日：1977-05-17
申请号：US609942
申请日：1975-09-03
申请人： William M. Herring , James P. Johnson , Dennis B. Walling
发明人： William M. Herring , James P. Johnson , Dennis B. Walling
IPC分类号： H04L12/40 , H04L25/26 , H04Q1/00
CPC分类号： H04L12/40032 , H04L25/26
摘要： A line driver system for digital communication, using logic-level voltages, between an electronic transmitter-receiver device and an electronic receiver device, such as between a computer and a typewriter, a line printer or a cathode ray tube, has the transmitter-receiver device at a location remote from the receiver device. An output of the transmitter-receiver device is electronically coupled to an input of the receiver device using one line of a communications bus. This output of the transmitter-receiver device is coupled to that line of the bus through an optical isolator and then through a power booster. The receiver device has an output that provides a voltage signal when the receiver device is switched on-line. This voltage signal is provided at that output of the receiver device when the receiver device is capable of transforming digital information, that is provided at its input, to a readable form that is printed or displayed by the receiver device. This output of the receiver device is coupled through another optical isolator and through another power booster to a second line of the bus so that this second line of the bus receives a voltage signal when the receiver device is in the on-line condition. This second line of the bus is electronically coupled to an input of the transmitter-receiver device that senses the presence of this signal at that input prior to initiating a transmittal of digital information as logic-level voltages to the first line of the bus to provide logic-level voltages at the input of the receiver device. Each power booster has a high current gain amplifier with unity voltage gain. When the receiver device is also a transmitter device another output of the receiver device is electronically coupled through an optical isolator and a further power booster to a third line of the bus that is electronically coupled to another input of the transmitter-receiver device so that digital information as logic-level voltages are received from the receiver device by the transmitter-receiver device.

4. 发明授权

US3967095A Multi-counter register 失效
公开(公告)号：US3967095A
公开(公告)日：1976-06-29
申请号：US500321
申请日：1974-08-26
申请人： William M. Herring , Dennis B. Walling
发明人： William M. Herring , Dennis B. Walling
IPC分类号： H03K21/00 , H03K21/12 , H03K21/18
CPC分类号： H03K21/18 , H03K21/00 , H03K21/12
摘要： At the general area of a set of BCD counter means, each to contain individual accumulated counts, a system, called a multi-counter register, is generally located for its use that permits the individual reading of the counter means in a selective mode by local readout means at the general area or by a computer at a remote area by the use of a small number of address channels extending from the location of the counter means to the computer. The multi-counter register includes data storage means, having inputs to receive digital information and having outputs to transmit that digital information, sets of gate means that are connected in parallel at their outputs to these inputs of the storage means and that have their inputs connectable to different BCD counter means, means responsive to signals, including signals providing digital information, to enable selectively one of said sets of gate means so that the BCD counter means connected to that enabled set of gate means is operatively connected to said inputs of said data storage means for transfer of digital information from that BCD counter means to said storage means when it can be loaded, said signal-responsive means being operatively connected to said sets of gate means, and means to provide at least one signal to another input of said storage means so that it can be loaded at said inputs, connected to said sets of gate means, with the digital information in that BCD counter means connected to that set of gate means enabled by said signal-responsive means, said signal-providing means being operatively connected to said another input of said storage means. In one construction of the invention, in which there is selection and readout by a computer, the information entered into the storage means of the multi-counter register from one of the counter means is transmittted serially to the computer. Illustratively in that construction the storage means is shift register means. In another construction of the invention the information is transmitted in a parallel manner from the storage means of the multi-counter register to the computer. Illustratively in that construction the storage means includes data latch means. The system, when having computer selection and readout, can include local readout means. In that case, there are means for manual interrogation of any desired counter means and means to prevent the operation of the manual interrogation during the operation by the computer of the multi-counter register through the operations of enabling selected sets of gate means by the signal-responsive means, enabling the storage means to be loaded with information in the counter means, and transmitting the digital information to the computer.

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