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1. 发明申请

US20070182463A1 Area efficient programmable frequency divider 有权
公开(公告)号：US20070182463A1
公开(公告)日：2007-08-09
申请号：US11213436
申请日：2005-08-26
申请人： Kallol Chatterjee , Deependra Jain
发明人： Kallol Chatterjee , Deependra Jain
IPC分类号： H03K23/00
CPC分类号： H03K23/665 , H03K21/40 , H03K23/667
摘要： A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.

2. 发明授权

US08093929B2 Programmable digital clock signal frequency divider module and modular divider circuit 有权
标题翻译：可编程数字时钟信号分频模块和模分频电路
公开(公告)号：US08093929B2
公开(公告)日：2012-01-10
申请号：US12715396
申请日：2010-03-02
申请人： Ankesh Jain , Deependra Jain , Krishna Thakur
发明人： Ankesh Jain , Deependra Jain , Krishna Thakur
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K21/00
摘要： A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output.
摘要翻译：可编程数字时钟信号分频器模块具有模块时钟输入，模块时钟输出，缩放因子输入，两个编程输入和三次输入。具有主分频器模块输出和时钟输入的主分频器模块耦合到模块时钟输入。次分频器模块包括多路复用器和由两个锁存器除以锁存时钟输入，耦合到主分频器模块输出。在操作中，应用于缩放因子输入和编程输入的逻辑值导致主分配器模块将主数字时钟信号的第一序列周期处理为第一基本时钟信号并且处理后续的第二次循环序列第二基本时钟信号。第一基本时钟信号和第二基本时钟信号向次级分频器模块提供时钟脉冲序列。时钟脉冲序列的边沿触发了两个锁存器的分频，这导致锁存输出时钟信号在分频输出端有两个锁存器，占空比为50％。第三输入的逻辑值选择时钟脉冲序列或锁存器输出时钟信号，作为模块时钟输出端的模块时钟输出信号。

3. 发明授权

US07304513B2 Area efficient programmable frequency divider 有权
标题翻译：区域效率可编程分频器
公开(公告)号：US07304513B2
公开(公告)日：2007-12-04
申请号：US11213436
申请日：2005-08-26
申请人： Kallol Chatterjee , Deependra Jain
发明人： Kallol Chatterjee , Deependra Jain
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/665 , H03K21/40 , H03K23/667
摘要： A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.
摘要翻译：提供了一种可编程高速分频器，其中用于形成能够以可编程分频比编程的分频器的级被简化以便减小面积和电路复杂度。可编程分频器包括耦合到逻辑检测电路的输出的第一同步元件，用于产生同步的分频器输出;耦合到逻辑检测电路的输出的附加同步元件，用于从分频输出接收其时钟两个电路并产生一个特殊的同步负载输出，以及接收负载输出的组合逻辑块，并产生位单元的负载信号，以检测所有级的状态。优选地，启动电路包括在分频器内，以确保分频器不会进入假状态。

4. 发明申请

US20070200641A1 SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION 有权
标题翻译：多相时钟生成系统与方法
公开(公告)号：US20070200641A1
公开(公告)日：2007-08-30
申请号：US11616742
申请日：2006-12-27
申请人： Tanmoy Sen , Anand Kumar , Deependra Jain
发明人： Tanmoy Sen , Anand Kumar , Deependra Jain
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K3/03 , H03K5/15013 , H03K5/15026 , H03K5/1506 , H03K2005/00241 , H03K2005/00247 , H03L7/095 , H03L7/0995 , Y10S331/02
摘要： A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.
摘要翻译：多相时钟电路包括多级压控振荡器（VCO）和多个时钟分频器。 VCO的工作频率高于所需输出频率的“N”倍，并产生具有不同相位但相同频率的“M”等间距输出，发送到多个时钟分频器。修改后的约翰逊计数器用作时钟分频器。每个计数器将时钟信号的频率除以N.结果，VCO的M个输出中的每一个被分成N个输出，从而形成总共“M×N”个等间隔的输出。这些输出时钟脉冲具有相同的频率但不同的相位。在该装置内提供一个顺序逻辑，用于一旦VCO开始输出输出就能使约翰逊计数器得以实现，从而保持约翰逊计数器的输出顺序。

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