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1. 发明申请

US20120327042A1 STYLUS ORIENTATION DETECTION 有权
标题翻译： STYLUS方位检测
公开(公告)号：US20120327042A1
公开(公告)日：2012-12-27
申请号：US13166743
申请日：2011-06-22
申请人： Jonah A. HARLEY , Li-Quan TAN , Debanjan MUKHERJEE , Steven Porter HOTELLING
发明人： Jonah A. HARLEY , Li-Quan TAN , Debanjan MUKHERJEE , Steven Porter HOTELLING
IPC分类号： G06F3/033
CPC分类号： G06F3/044 , G06F3/03545
摘要： Stylus orientation detection is disclosed. In an example, the orientation of a stylus relative to a contacting surface, e.g., a touch panel, can be detected by detecting a capacitance at one or more locations on the stylus relative to the surface, and then using the capacitance(s) to determine the orientation of the stylus relative to the surface. In another example, the orientation of a stylus relative to a contacting surface, e.g., a touch panel, can be detected by first detecting the orientation of the stylus relative to a reference, detecting the orientation of the contacting surface relative to the reference, and then calculating the orientation of the stylus relative to the contacting surface using the two detected orientations.
摘要翻译：披露了触笔取向检测。在一个示例中，触针相对于接触表面（例如触摸面板）的取向可以通过检测触针上相对于表面的一个或多个位置处的电容来检测，然后使用电容确定触控笔相对于表面的方向。在另一示例中，触针相对于接触表面（例如触摸面板）的取向可以通过首先检测触针相对于基准的取向，检测接触表面相对于基准的取向来检测，以及然后使用两个检测到的取向计算触针相对于接触表面的取向。

2. 发明授权

US07266145B2 Adaptive signal equalizer with adaptive error timing and precursor/postcursor configuration control 有权
标题翻译：自适应信号均衡器，具有自适应误差定时和前置/后端配置控制
公开(公告)号：US07266145B2
公开(公告)日：2007-09-04
申请号：US10321876
申请日：2002-12-17
申请人： Venugopal Balasubramonian , Jishnu Bhattacharjee , Edem Ibragimov , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Qian Yu
发明人： Venugopal Balasubramonian , Jishnu Bhattacharjee , Edem Ibragimov , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Qian Yu
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03H21/0012 , H03H2021/0096 , H04L7/0029 , H04L7/0062 , H04L7/0079 , H04L2025/0349 , H04L2025/03611
摘要： An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.
摘要翻译：一种具有前馈滤波器的自适应信号均衡器，其中反馈误差信号和相应的输入数据信号在时间上使用信号插值动态对准，此外，控制前驱/后沿滤波器抽头配置，由此产生更多的自适应滤波器抽头系数信号，显着改善和鲁棒的信号均衡。

3. 发明申请

US20070115074A1 Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain 有权
公开(公告)号：US20070115074A1
公开(公告)日：2007-05-24
申请号：US11640079
申请日：2006-12-15
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee
IPC分类号： H04B3/14
CPC分类号： H03F3/45183 , H03F2203/45631 , H03F2203/45638 , H03F2203/45652 , H03F2203/45688 , H03F2203/45712
摘要： A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.

4. 发明申请

US20060061415A1 Low voltage broadband gain cell 有权
标题翻译：低电压宽带增益电池
公开(公告)号：US20060061415A1
公开(公告)日：2006-03-23
申请号：US10946738
申请日：2004-09-21
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee
IPC分类号： G06G7/12
CPC分类号： H03F1/42 , H03F3/45183 , H03F3/45188 , H03F2200/39 , H03F2203/45361 , H03F2203/45638 , H03F2203/45641 , H03F2203/45652 , H03F2203/45686 , H03F2203/45702 , H03F2203/45704 , H03F2203/45706 , H03F2203/45731
摘要： T-coil structures are used in one embodiment to inject programmably-variable amounts of transistor biasing currents into the respective drains of current sinking transistor means of a broadband differential amplifier such that, when the differential amplifier is in common mode, total transistor drain current will exceed total voltage-dropping current passing through corresponding voltage-dropping resistances of the amplifier's transistor means. The T-coil structures keep the parasitic capacitances of the programmable current sources that provide the bias currents de-lumped from capacitances of the amplifier's output nodes and/or capacitances of the amplifier's voltage-dropping resistances (variable resistances) to thereby maintain a wide bandwidth.
摘要翻译：在一个实施例中使用T形线圈结构，以将可编程可变量的晶体管偏置电流注入到宽带差分放大器的电流吸收晶体管装置的相应漏极中，使得当差分放大器处于共模时，总晶体管漏极电流将超过通过放大器晶体管装置的相应降压电阻的总压降电流。 T线圈结构保持可编程电流源的寄生电容，其提供从放大器的输出节点的电容和/或放大器的降压电阻（可变电阻）的电容中解除的偏置电流，从而保持宽带宽。

5. 发明授权

US06965337B1 Reference generator 有权
标题翻译：参考发生器
公开(公告)号：US06965337B1
公开(公告)日：2005-11-15
申请号：US10899498
申请日：2004-07-26
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Fabian Giroud
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Fabian Giroud
IPC分类号： H03K5/24 , H03M1/12
CPC分类号： H03K5/2481
摘要： Systems and methods are disclosed herein to provide reference generators. For example, in accordance with an embodiment of the present invention, a reference generator is provided for an electrical device, such as for example for an analog-to-digital converter. The reference generator may provide one or more reference signals having a common mode voltage that can track or be varied based on a common mode voltage of an input signal. Alternatively or in addition, the reference generator may provide reference signals for single-ended applications.
摘要翻译：本文公开了系统和方法以提供参考发生器。例如，根据本发明的实施例，为电气设备提供参考发生器，例如用于模数转换器。参考发生器可以提供具有可以基于输入信号的共模电压跟踪或变化的共模电压的一个或多个参考信号。或者或另外，参考发生器可为单端应用提供参考信号。

6. 发明授权

US06952132B2 Method and apparatus for automatic gain control 有权
公开(公告)号：US06952132B2
公开(公告)日：2005-10-04
申请号：US10724444
申请日：2003-11-26
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
IPC分类号： H03G3/00 , H03G3/30 , H03G3/20
CPC分类号： H03G3/30 , H03G3/001
摘要： Systems and methods provide automatic gain control, such as by employing analog and digital techniques. For example, overall gain may be controlled through coarse and fine control signals provided to gain stages, with the overall gain monitored via a power detector circuit.

7. 发明申请

US20050104158A1 COMPACT, HIGH Q INDUCTOR FOR INTEGRATED CIRCUIT 审中-公开
标题翻译： COMPACT，用于集成电路的高Q电感器
公开(公告)号：US20050104158A1
公开(公告)日：2005-05-19
申请号：US10718501
申请日：2003-11-19
申请人： Jishnu Bhattacharjee , Madabusi Govindarajan , Debanjan Mukherjee , Abhijit Phanse , Prashant Choudhary
发明人： Jishnu Bhattacharjee , Madabusi Govindarajan , Debanjan Mukherjee , Abhijit Phanse , Prashant Choudhary
IPC分类号： H01L21/02 , H01L23/522 , H01L29/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor for an integrated circuit made of a plurality of stacked, electrically coupled, metal layers. Each metal layer includes an inductor formed of a spiral pattern, which except for the top and bottom inductors, are electrically coupled to the spiral inductor formed on the metal layer above and below with an electrical path or via formed between each metal layer. The top and bottom inductors are electrically coupled to the inductor directly below and above, respectively.
摘要翻译：一种用于由多个堆叠的电耦合的金属层制成的集成电路的电感器。每个金属层包括由螺旋图案形成的电感器，除了顶部和底部电感器之外，通过在每个金属层之间形成的电路径或通孔电连接到形成在金属层上的螺旋电感器上方和下方。顶部和底部电感器分别电连接到电感器上方。

8. 发明授权

US08918665B2 Operating input device in low power mode with auxiliary sensor calibrated to main sensor 有权
标题翻译：操作输入设备在低功率模式下，辅助传感器校准到主传感器
公开(公告)号：US08918665B2
公开(公告)日：2014-12-23
申请号：US13244020
申请日：2011-09-23
申请人： Wing Kong Low , Debanjan Mukherjee
发明人： Wing Kong Low , Debanjan Mukherjee
IPC分类号： G06F1/32
CPC分类号： G06F1/3259 , G06F1/3234 , G06F3/033 , Y02D10/155
摘要： An input device for an electronic device. The input device includes a power source, a processor in communication with the power source. Additionally, the input device includes a main sensor in communication with processor and configured to detect a user input and an auxiliary sensor in communication with the processor and configured to detect a user input. When the input device is in a normal power mode or active state, the main sensor is activated and when the input device is in a low power state the main sensor is deactivate and the auxiliary sensor is activated.
摘要翻译：一种用于电子设备的输入设备。输入装置包括电源，与电源通信的处理器。另外，输入设备包括与处理器通信并被配置为检测用户输入的主传感器和与处理器通信的辅助传感器，并且被配置为检测用户输入。当输入设备处于正常电源模式或有效状态时，主传感器被激活，当输入设备处于低功率状态时，主传感器被禁用，辅助传感器被激活。

9. 发明授权

US07627031B2 Adaptive signal latency control for communications systems signals 有权
标题翻译：通信系统信号的自适应信号延迟控制
公开(公告)号：US07627031B2
公开(公告)日：2009-12-01
申请号：US11186241
申请日：2005-07-21
申请人： Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Edem Ibragimov , Fabian Giroud
发明人： Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse , Abhijit G. Shanbhag , Edem Ibragimov , Fabian Giroud
IPC分类号： H03H7/30
CPC分类号： H04L7/0062 , H04L7/0029 , H04L25/03057 , H04L2025/03503
摘要： An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.
摘要翻译：一种用于自适应地引入与数据符号判定电路的信号等待时间相关的补偿信号延迟的装置和方法。自适应定时控制电路，包括实现为具有相关抽头系数的抽头延迟线的内插混频器，自适应地和基本上匹配数据判决电路的等待时间以在自适应均衡器内使用，从而最小化这样的均方误差决策电路。该自适应等待时间用于产生反馈误差信号，反馈误差信号又可由前馈均衡器用于动态调整其自适应滤波器抽头系数。

10. 发明授权

US07190226B2 Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain 有权
标题翻译：具有更均匀分布的容性负载的模拟延迟链和用于链中的模拟延迟单元
公开(公告)号：US07190226B2
公开(公告)日：2007-03-13
申请号：US10928420
申请日：2004-08-27
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2203/45631 , H03F2203/45638 , H03F2203/45652 , H03F2203/45688 , H03F2203/45712
摘要： A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.
摘要翻译：抽头延迟链包括多个延迟单元，其中每个单元具有至少两个输出抽头：用于将延迟的信号馈送到链中的下一个单元的初级延迟单元，以及用于馈送稍微不同的延迟信号的次级输出抽头到乘法器单元，使得略微不同的延迟信号可以乘以加权系数。每个延迟单元中的输出抽头分开允许相应的负载电容分流。延迟单元的每个输出抽头加载的电容小于如果分裂抽头被集中在一起作为公共节点而不得不以其他方式驱动的电容。每个分接抽头的减小的负载电容允许更宽的频率响应范围。抽头延迟链可用于形成前馈均衡器（FFE），该前馈均衡器还包括加法器和多个乘法器，每个乘法器分别接收延迟的输入信号（（延迟））链中相应的延迟单元的辅助输出抽头，并且每个输出相应的延迟加权乘积信号（Pi）给加法器。

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