专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08605826B2 Multi-gigabit millimeter wave receiver system and demodulator system 有权
标题翻译：多千兆毫米波接收机系统和解调器系统
公开(公告)号：US08605826B2
公开(公告)日：2013-12-10
申请号：US12850481
申请日：2010-08-04
申请人： Eric Juntunen , Stephane Pinel , Joy Laskar , David Yeh , Saikat Sarkar
发明人： Eric Juntunen , Stephane Pinel , Joy Laskar , David Yeh , Saikat Sarkar
IPC分类号： H04L27/14 , H04L27/16 , H04L27/22
CPC分类号： H04B1/16 , H03D7/125 , H03D2200/0074 , H04B1/30
摘要： A receiver system and a demodulator system are configured to receive and demodulate, respectively, multi-gigabit millimeter wave signals being wirelessly transmitted in the unlicensed wireless band near 60 GHz.
摘要翻译：接收机系统和解调器系统被配置为分别接收和解调在60GHz附近的未经许可的无线频带中无线发送的千兆位毫米波信号。

2. 发明申请

US20110207425A1 MULTI-GIGABIT MILLIMETER WAVE RECEIVER SYSTEM AND DEMODULATOR SYSTEM 有权
标题翻译：多功能千兆接收机系统和解调器系统
公开(公告)号：US20110207425A1
公开(公告)日：2011-08-25
申请号：US12850481
申请日：2010-08-04
申请人： Eric JUNTUNEN , Stephane PINEL , Joy LASKAR , David YEH , Saikat SARKAR
发明人： Eric JUNTUNEN , Stephane PINEL , Joy LASKAR , David YEH , Saikat SARKAR
IPC分类号： H04W88/02
CPC分类号： H04B1/16 , H03D7/125 , H03D2200/0074 , H04B1/30
摘要： A receiver system and a demodulator system are configured to receive and demodulate, respectively, multi-gigabit millimeter wave signals being wirelessly transmitted in the unlicensed wireless band near 60 GHz.
摘要翻译：接收机系统和解调器系统被配置为分别接收和解调在60GHz附近的未经许可的无线频带中无线发送的千兆位毫米波信号。

3. 发明申请

US20100093299A1 ANALOG SIGNAL PROCESSOR IN A MULTI-GIGABIT RECEIVER SYSTEM 有权
标题翻译：多功能接收机系统中的模拟信号处理器
公开(公告)号：US20100093299A1
公开(公告)日：2010-04-15
申请号：US12447163
申请日：2007-10-25
申请人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
发明人： Stephane Pinel , Joy Laskar , David Yeh , Bevin George Perumana , Saikat Sarkar
IPC分类号： H04B17/00 , H04B1/16
CPC分类号： G06G7/12
摘要： An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.
摘要翻译：可以实现模拟多吉比特接收机和/或收发机用于使用CMOS（互补金属氧化物半导体）工艺调制的多吉比特正交相移键控（QPSK）的接收和解调。此外，可以实现模拟多吉比特接收机和/或收发器用于接收和解调多吉比特二进制相移键控（BPSK），最小移位键控（MSK）和/或幅度键控（ASK）信号调制在CMOS工艺中。

4. 发明授权

US07589796B2 Video display device, video encoder, and methods for use therewith 有权
标题翻译：视频显示设备，视频编码器和与其一起使用的方法
公开(公告)号：US07589796B2
公开(公告)日：2009-09-15
申请号：US11348120
申请日：2006-02-06
申请人： Xinghai (Billy) Li , Chun-Chin (David) Yeh , Xu Gang (Wilf) Zhao
发明人： Xinghai (Billy) Li , Chun-Chin (David) Yeh , Xu Gang (Wilf) Zhao
IPC分类号： H04N7/32
CPC分类号： H04N5/4401 , H04N5/44591 , H04N5/45 , H04N19/117 , H04N19/137 , H04N19/16 , H04N19/176 , H04N19/44 , H04N19/80 , H04N19/85 , H04N21/44008
摘要： A video encoder includes a receiving module for receiving a video signal, the video signal including a plurality of fields, wherein each of the plurality of fields includes a plurality of pixels. The video encoder further includes a signal processor having a signal processing module for generating a processed video signal and a video encoding module for producing an encoded video signal based on the processed video signal. The signal processing module includes a video filter module that is enabled when a filter enable signal is asserted and disabled when the filter enable signal is deasserted. The video filter module filters at least one of the plurality of pixels of a corresponding one of the plurality of fields when the video filter module is enabled. The signal processor also includes a filter enable module for generating the filter enable signal, the filter enable module including a motion detection module for detecting motion in the at least one of the plurality of pixels and for deasserting the filter enable signal when motion is detected in the at least one of the plurality of pixels.
摘要翻译：视频编码器包括用于接收视频信号的接收模块，所述视频信号包括多个场，其中所述多个场中的每一个包括多个像素。视频编码器还包括信号处理器，具有用于产生经处理的视频信号的信号处理模块和用于基于经处理的视频信号产生编码视频信号的视频编码模块。信号处理模块包括视频滤波器模块，当滤波器使能信号被断言时，当滤波器使能信号被断言并被禁止时被使能。当视频滤波器模块被使能时，视频滤波器模块对多个场中相应一个的多个像素中的至少一个像素进行滤波。所述信号处理器还包括用于产生所述滤波器使能信号的滤波器使能模块，所述滤波器使能模块包括用于检测所述多个像素中的至少一个像素中的运动的运动检测模块，以及当在所述滤波器使能信号中检测到运动时解除所述滤波器使能信号所述多个像素中的至少一个。

5. 发明授权

US07365757B1 Method and apparatus for independent video and graphics scaling in a video graphics system 有权
标题翻译：用于在视频图形系统中独立视频和图形缩放的方法和装置
公开(公告)号：US07365757B1
公开(公告)日：2008-04-29
申请号：US09213748
申请日：1998-12-17
申请人： Edward G. Callway , Allen J. C. Porter , Chun-Chin David Yeh , Philip L. Swan
发明人： Edward G. Callway , Allen J. C. Porter , Chun-Chin David Yeh , Philip L. Swan
IPC分类号： G09G5/00 , H04N9/74
CPC分类号： G09G5/397 , G09G2320/0247 , G09G2340/0407 , G09G2340/125 , G09G2370/042
摘要： A method and apparatus for independent video and graphics scaling in a video graphics system is accomplished by receiving a video data stream, wherein the video data stream includes video data in a first format. A graphics data stream is also received, and the graphics data stream includes graphics data in a second format. The video data of the video data stream is scaled based on a ratio between the first format and a selected video format to produce a scaled video stream. Similarly, the graphics data of the graphics data stream is scaled based on a ratio between the second format and a selected graphics format in order to produce a scaled graphics stream. The scaled video stream and the scaled graphics stream are then merged to produce a video graphics output stream.
摘要翻译：通过接收视频数据流来实现视频图形系统中的独立视频和图形缩放的方法和装置，其中视频数据流包括第一格式的视频数据。还接收图形数据流，并且图形数据流包括第二格式的图形数据。基于第一格式和所选视频格式之间的比率来缩放视频数据流的视频数据，以产生缩放的视频流。类似地，图形数据流的图形数据基于第二格式和所选图形格式之间的比例进行缩放，以便产生缩放的图形流。缩放的视频流和缩放的图形流然后被合并以产生视频图形输出流。

6. 发明申请

US20140319623A1 METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS 审中-公开
标题翻译：在三极（FINFET）工艺上集成多个栅极介质晶体管的方法
公开(公告)号：US20140319623A1
公开(公告)日：2014-10-30
申请号：US13997624
申请日：2011-12-28
申请人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
发明人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
IPC分类号： H01L21/8234 , H01L29/423 , H01L27/088
摘要： Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
摘要翻译：描述了具有不同栅极结构并形成在单个集成电路上的两种或多种类型的鳍式晶体管。每种类型的晶体管的栅极结构至少区别于栅极电介质层的厚度或组成或栅电极中功函数金属层的组成。还提供了用于制造具有至少两种不同类型的基于鳍的晶体管的集成电路的方法，其中晶体管类型通过栅极电介质层的厚度和组成和/或工件的厚度和组成来区分功能金属在栅电极。

7. 发明授权

US07667776B2 Video display device, video encoder, noise level estimation module and methods for use therewith 有权
标题翻译：视频显示装置，视频编码器，噪声电平估计模块及其使用方法
公开(公告)号：US07667776B2
公开(公告)日：2010-02-23
申请号：US11348119
申请日：2006-02-06
申请人： Xinghai (Billy) Li , Xu Gang (Wilf) Zhao , Chun-Chin (David) Yeh
发明人： Xinghai (Billy) Li , Xu Gang (Wilf) Zhao , Chun-Chin (David) Yeh
IPC分类号： H04N5/21 , H04N7/12
CPC分类号： H04N5/21 , H04N5/147 , H04N17/00
摘要： A noise level estimation module includes a pixel block selection module for selecting a plurality of selected pixel blocks over a set of K fields of a video signal, each of the plurality of selected pixel blocks containing a plurality of pixels having corresponding pixel values. A difference calculation module calculates a block difference for each of the plurality of selected pixel blocks based on a pixel difference between the pixel value for each of the plurality of pixels and a pixel value for a corresponding pixel in an adjacent field. A signal generator generates a noise level estimation signal based on a subset of M block differences for the plurality of pixel blocks, wherein M is greater than one.
摘要翻译：噪声电平估计模块包括：像素块选择模块，用于在视频信号的K个场的集合上选择多个选择的像素块，所述多个所选择的像素块中的每一个包含具有相应像素值的多个像素。差分计算模块基于多个像素中的每一个的像素值与相邻像素中的相应像素的像素值之间的像素差来计算多个所选像素块中的每一个的块差。信号发生器基于多个像素块的M个块差异的子集产生噪声电平估计信号，其中M大于1。

8. 发明申请

US20090001415A1 MULTI-GATE TRANSISTOR WITH STRAINED BODY 审中-公开
标题翻译：具有应变体的多栅极晶体管
公开(公告)号：US20090001415A1
公开(公告)日：2009-01-01
申请号：US11772199
申请日：2007-06-30
申请人： Nick Lindert , Walid Mac Hafez , Jeng-Ya David Yeh
发明人： Nick Lindert , Walid Mac Hafez , Jeng-Ya David Yeh
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A semiconductor device comprises a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate, wherein the semiconductor body comprises a silicon alloy core having a top surface and laterally opposite sidewalls formed on a silicon fin structure, and a silicon shell layer formed on the top surface and the laterally opposite sidewalls of the silicon alloy core, wherein the silicon alloy core imparts a strain on the silicon shell layer. The semiconductor device further comprises a gate dielectric layer formed on the top surface and the laterally opposite sidewalls of the semiconductor body and a gate electrode formed on the gate dielectric layer.
摘要翻译：半导体器件包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁，其中半导体本体包括硅合金芯，其具有形成在硅鳍结构上的顶表面和横向相对的侧壁，并且形成硅壳层在硅合金芯的顶表面和横向相对的侧壁上，其中硅合金芯在硅壳层上施加应变。半导体器件还包括形成在半导体主体的顶表面和横向相对的侧壁上的栅介质层和形成在栅介质层上的栅电极。

9. 发明申请

US20070183512A1 Video display device, video encoder, and methods for use therewith 有权
标题翻译：视频显示设备，视频编码器和与其一起使用的方法
公开(公告)号：US20070183512A1
公开(公告)日：2007-08-09
申请号：US11348120
申请日：2006-02-06
申请人： Xinghai (Billy) Li , Chun-Chin (David) Yeh , Xu Gang (Wilf) Zhao
发明人： Xinghai (Billy) Li , Chun-Chin (David) Yeh , Xu Gang (Wilf) Zhao
IPC分类号： H04B1/66
CPC分类号： H04N5/4401 , H04N5/44591 , H04N5/45 , H04N19/117 , H04N19/137 , H04N19/16 , H04N19/176 , H04N19/44 , H04N19/80 , H04N19/85 , H04N21/44008
摘要： A video encoder includes a receiving module for receiving a video signal, the video signal including a plurality of fields, wherein each of the plurality of fields includes a plurality of pixels. The video encoder further includes a signal processor having a signal processing module for generating a processed video signal and a video encoding module for producing an encoded video signal based on the processed video signal. The signal processing module includes a video filter module that is enabled when a filter enable signal is asserted and disabled when the filter enable signal is deasserted. The video filter module filters at least one of the plurality of pixels of a corresponding one of the plurality of fields when the video filter module is enabled. The signal processor also includes a filter enable module for generating the filter enable signal, the filter enable module including a motion detection module for detecting motion in the at least one of the plurality of pixels and for deasserting the filter enable signal when motion is detected in the at least one of the plurality of pixels.
摘要翻译：视频编码器包括用于接收视频信号的接收模块，所述视频信号包括多个场，其中所述多个场中的每一个包括多个像素。视频编码器还包括信号处理器，具有用于产生经处理的视频信号的信号处理模块和用于基于经处理的视频信号产生编码视频信号的视频编码模块。信号处理模块包括视频滤波器模块，当滤波器使能信号被断言时，当滤波器使能信号被断言并被禁止时被使能。当视频滤波器模块被使能时，视频滤波器模块对多个场中相应一个的多个像素中的至少一个像素进行滤波。所述信号处理器还包括用于产生所述滤波器使能信号的滤波器使能模块，所述滤波器使能模块包括用于检测所述多个像素中的至少一个像素中的运动的运动检测模块，以及当在所述滤波器使能信号中检测到运动时解除所述滤波器使能信号所述多个像素中的至少一个。

10. 外观设计

USD655296S1 Electronic device 有权
公开(公告)号：USD655296S1
公开(公告)日：2012-03-06
申请号：US29388897
申请日：2011-04-04
申请人： Bartley K. Andre , John M. Brock , Matthew Phillip Casebolt , Brett William Degner , Ron Alan Hopkinson , Eugene Kim , Chris Ligtenberg , John Raff , David Yeh
设计人： Bartley K. Andre , John M. Brock , Matthew Phillip Casebolt , Brett William Degner , Ron Alan Hopkinson , Eugene Kim , Chris Ligtenberg , John Raff , David Yeh

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式