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    • 2. 发明授权
    • Interrupt processing in a data processing system
    • 数据处理系统中的中断处理
    • US06892260B2
    • 2005-05-10
    • US09998506
    • 2001-11-30
    • David P. Burgess
    • David P. Burgess
    • G06F9/30G06F9/308G06F9/312G06F9/32G06F9/38G06F9/48G06F13/24
    • G06F9/3842G06F9/30018G06F9/3004G06F9/30072G06F9/30087G06F9/30094G06F9/30101G06F9/3834G06F9/3836G06F9/3859
    • The present invention relates generally to interrupt processing. One embodiment relates to a method for executing an interrupt in a data processing system including fetching a conditional store instruction that is conditional upon a reservation, receiving notice that an interrupt is pending, invalidating a reservation in response to receiving the notice, and processing the interrupt. Invalidating the reservation allows the conditional store instruction to finish in a predetermined amount of time and properly update an architectural state of the processor. Therefore, interrupt latencies (the amount of time between receiving and processing an interrupt) corresponding to the conditional store instruction can be bounded. The method may be used in a single processor or multi-processor data processing system, wherein each processor includes a reservation register. Furthermore, each processor may include both a completion unit for storing instructions in the order they are issued and a store queue within a load/store unit.
    • 本发明一般涉及中断处理。 一个实施例涉及一种用于在数据处理系统中执行中断的方法,包括获取条件存储指令,该条件存储指令取决于预留,接收到中断待处理的通知,响应于接收到该通知而使保留无效,以及处理该中断 。 使预约无效允许条件存储指令在预定量的时间内完成,并且适当地更新处理器的架构状态。 因此,与条件存储指令相对应的中断延迟(接收和处理中断之间的时间量)可以是有界的。 该方法可以用在单处理器或多处理器数据处理系统中,其中每个处理器包括预留寄存器。 此外,每个处理器可以包括用于按照发出的顺序存储指令的完成单元和在加载/存储单元内的存储队列。