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1. 发明授权

US08468532B2 Adjusting CPU time allocated to next thread based on gathered data in heterogeneous processor system having plurality of different instruction set architectures 失效
标题翻译：基于在具有多个不同的指令集架构的异构处理器系统中收集的数据来调整分配给下一个线程的CPU时间
公开(公告)号：US08468532B2
公开(公告)日：2013-06-18
申请号：US11425448
申请日：2006-06-21
申请人： Maximino Aguilar, Jr. , David John Erb , Sidney James Manning , James Michael Stafford
发明人： Maximino Aguilar, Jr. , David John Erb , Sidney James Manning , James Michael Stafford
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F11/3409 , G06F2201/86 , G06F2209/483
摘要： A method that optimizes system performance using performance monitors is presented. The method gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.
摘要翻译：介绍了使用性能监视器优化系统性能的方法。该方法使用在第一ISA处理器或第二ISA处理器上运行的线程的性能监视器收集线程性能数据。多个第一处理器和多个第二处理器可以包括在单个计算机系统中。第一处理器和第二处理器可以各自访问存储在公共共享存储器中的数据。分析收集的线程性能数据，以确定相应的线程是否需要额外的CPU时间，以优化系统性能。如果需要额外的CPU时间，则线程接收的CPU时间量会被更改（增加），以便线程在调度程序调度时收到额外的时间。在一个实施例中，通过改变对应于线程的优先级值来实现增加的CPU时间。

2. 发明申请

US20070300231A1 SYSTEM AND METHOD FOR USING PERFORMANCE MONITOR TO OPTIMIZE SYSTEM PERFORMANCE 失效
标题翻译：使用性能监视器优化系统性能的系统和方法
公开(公告)号：US20070300231A1
公开(公告)日：2007-12-27
申请号：US11425448
申请日：2006-06-21
申请人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
发明人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F11/3409 , G06F2201/86 , G06F2209/483
摘要： A system, method, and program product that optimizes system performance using performance monitors is presented. The system gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.
摘要翻译：介绍了使用性能监视器优化系统性能的系统，方法和程序产品。系统使用在第一个ISA处理器或第二个ISA处理器上运行的线程的性能监视器收集线程性能数据。多个第一处理器和多个第二处理器可以包括在单个计算机系统中。第一处理器和第二处理器可以各自访问存储在公共共享存储器中的数据。分析收集的线程性能数据，以确定相应的线程是否需要额外的CPU时间，以优化系统性能。如果需要额外的CPU时间，则线程接收的CPU时间量会被更改（增加），以便线程在调度程序调度时收到额外的时间。在一个实施例中，通过改变对应于线程的优先级值来实现增加的CPU时间。

3. 发明授权

US07613912B2 System and method for simulating hardware interrupts 失效
标题翻译：用于模拟硬件中断的系统和方法
公开(公告)号：US07613912B2
公开(公告)日：2009-11-03
申请号：US11771688
申请日：2007-06-29
申请人： David John Erb
发明人： David John Erb
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F17/5022 , G06F8/445 , G06F9/30058 , G06F9/3836
摘要： A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a known memory area. In one embodiment, the processor has at least two pipelines that need to be aligned so that certain instructions are scheduled for the first pipeline and other instructions are scheduled for the other. In this embodiment, the BISLED also serves the purpose of re-aligning the instruction stream so that instructions are placed in the correct pipeline based upon the function performed by the instruction.
摘要翻译：提供了一种系统和方法，用于通过将指令插入到通常插入“无操作”（或NOOP））指令的指令流中来模拟硬件中断。插入指令是称为BISLED的条件分支指令，如果在已知存储区域中存在外部数据，则该指令将分支。在一个实施例中，处理器具有至少两条需要对齐的管线，以便为第一流水线调度某些指令，而为其他指令调度其他指令。在该实施例中，BISLED还用于重新对准指令流的目的，使得根据指令执行的功能将指令置于正确的流水线中。

4. 发明申请

US20080163240A1 Using Performance Monitor to Optimize System Performance 审中-公开
标题翻译：使用性能监视器优化系统性能
公开(公告)号：US20080163240A1
公开(公告)日：2008-07-03
申请号：US12049285
申请日：2008-03-15
申请人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
发明人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F11/3409 , G06F2201/86 , G06F2209/483
摘要： An approach that optimizes system performance using performance monitors is presented. The system gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.
摘要翻译：介绍了使用性能监视器优化系统性能的方法。系统使用在第一个ISA处理器或第二个ISA处理器上运行的线程的性能监视器收集线程性能数据。多个第一处理器和多个第二处理器可以包括在单个计算机系统中。第一处理器和第二处理器可以各自访问存储在公共共享存储器中的数据。分析收集的线程性能数据，以确定相应的线程是否需要额外的CPU时间，以优化系统性能。如果需要额外的CPU时间，则线程接收的CPU时间量会被更改（增加），以便线程在调度程序调度时收到额外的时间。在一个实施例中，通过改变对应于线程的优先级值来实现增加的CPU时间。

5. 发明授权

US07707560B2 Analyzing software performance without requiring hardware 失效
标题翻译：分析软件性能而不需要硬件
公开(公告)号：US07707560B2
公开(公告)日：2010-04-27
申请号：US12049309
申请日：2008-03-15
申请人： David John Erb
发明人： David John Erb
IPC分类号： G06F9/44
CPC分类号： G06F11/3447 , G06F11/3419 , G06F2201/865 , G06F2201/88
摘要： An approach of analyzing software performance without requiring hardware is presented. A timing description generator logs instruction performance characteristics for each of the assembly code's instructions. The performance characteristics identify whether an instruction issued or stalled during particular instruction cycles. Once the timing description generator cycles through the instructions and logs performance characteristics for each instruction, the timing description generator generates a performance graph. For each page line, the performance graph includes 1) dual-issue information if applicable, 2) instruction cycle counter values/stalled instruction identifier's that are positioned at corresponding line location values, and 3) the instruction. A developer may analyze the performance graph and identify code locations that require optimization in order to increase performance.
摘要翻译：提出了一种在不需要硬件的情况下分析软件性能的方法。定时描述生成器记录每个汇编代码指令的指令性能特征。性能特征识别在特定指令周期期间发出或停止的指令。一旦定时描述生成器循环执行指令并记录每个指令的性能特征，定时描述生成器生成一个性能图。对于每个页面行，性能图包括1）双重问题信息（如果适用）2）指令周期计数器值/停止的指令标识符位于相应的行位置值，以及3）指令。开发人员可以分析性能图表并识别需要优化的代码位置，以提高性能。

6. 发明申请

US20080162108A1 Analyzing Software Performance Without Requiring Hardware 失效
标题翻译：分析软件性能，无需硬件
公开(公告)号：US20080162108A1
公开(公告)日：2008-07-03
申请号：US12049309
申请日：2008-03-15
申请人： David John Erb
发明人： David John Erb
IPC分类号： G06F9/00
CPC分类号： G06F11/3447 , G06F11/3419 , G06F2201/865 , G06F2201/88
摘要： An approach of analyzing software performance without requiring hardware is presented. A timing description generator logs instruction performance characteristics for each of the assembly code's instructions. The performance characteristics identify whether an instruction issued or stalled during particular instruction cycles. Once the timing description generator cycles through the instructions and logs performance characteristics for each instruction, the timing description generator generates a performance graph. For each page line, the performance graph includes 1) dual-issue information if applicable, 2) instruction cycle counter values/stalled instruction identifier's that are positioned at corresponding line location values, and 3) the instruction. A developer may analyze the performance graph and identify code locations that require optimization in order to increase performance.
摘要翻译：提出了一种在不需要硬件的情况下分析软件性能的方法。定时描述生成器记录每个汇编代码指令的指令性能特征。性能特征识别在特定指令周期期间发出或停止的指令。一旦定时描述生成器循环执行指令并记录每个指令的性能特征，定时描述生成器生成一个性能图。对于每个页面行，性能图包括1）双重问题信息（如果适用）2）指令周期计数器值/停止的指令标识符位于相应的行位置值，以及3）指令。开发人员可以分析性能图表并识别需要优化的代码位置，以提高性能。

7. 发明授权

US07278014B2 System and method for simulating hardware interrupts 失效
标题翻译：用于模拟硬件中断的系统和方法
公开(公告)号：US07278014B2
公开(公告)日：2007-10-02
申请号：US11002533
申请日：2004-12-02
申请人： David John Erb
发明人： David John Erb
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F17/5022 , G06F8/445 , G06F9/30058 , G06F9/3836
摘要： A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a known memory area. In one embodiment, the processor has at least two pipelines that need to be aligned so that certain instructions are scheduled for the first pipeline and other instructions are scheduled for the other. In this embodiment, the BISLED also serves the purpose of re-aligning the instruction stream so that instructions are placed in the correct pipeline based upon the function performed by the instruction.
摘要翻译：提供了一种系统和方法，用于通过将指令插入到通常插入“无操作”（或NOOP））指令的指令流中来模拟硬件中断。插入指令是称为BISLED的条件分支指令，如果在已知存储区域中存在外部数据，则该指令将分支。在一个实施例中，处理器具有至少两条需要对齐的管线，以便为第一流水线调度某些指令，而为其他指令调度其他指令。在该实施例中，BISLED还用于重新对准指令流的目的，使得根据指令执行的功能将指令置于正确的流水线中。

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