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1. 发明授权

US07822955B2 Data processing apparatus and method for utilizing endianess independent data values 有权
标题翻译：数据处理装置和方法，用于使用端序独立数据值
公开(公告)号：US07822955B2
公开(公告)日：2010-10-26
申请号：US10347481
申请日：2003-01-21
申请人： David W Flynn , David J Seal , Wilco Dijkstra , Michael R Nonweiler
发明人： David W Flynn , David J Seal , Wilco Dijkstra , Michael R Nonweiler
IPC分类号： G06F7/00
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30076
摘要： The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be performed on particular sections of an input data word. The data processing apparatus of the present invention comprises a data processing unit for executing instructions which is responsive to the endian reverse instruction to apply an endian reverse operation to an input data word Rm comprising a plurality of data values. The endian reverse operation yields a result data word Rd given by: treating the input data word as consisting of a plurality of input sections, the result data word having a corresponding plurality of result sections, at least one input section comprising a plurality of data values; and for at least one of the input sections comprising a plurality of data values, performing an independent swap operation on the data values within that input section to form the result data word Rd in which the corresponding result section has its data values swapped with respect to that input section. This provides a particularly efficient technique for providing endian reversal functionality within a data processing apparatus supporting a variety of data structures, such as packed halfwords, zero extended halfwords, sign extended halfwords, etc.
摘要翻译：本发明提供了一种用于交换数据字中的数据值的技术。特别地，提供单个末端反向指令以使得对输入数据字的特定部分执行独立的交换操作。本发明的数据处理装置包括：数据处理单元，用于执行响应于末端反向指令的指令，以对包括多个数据值的输入数据字Rm应用结束反向操作。端序反转操作产生结果数据字Rd，其由下式给出：将输入数据字处理为由多个输入部分组成，结果数据字具有对应的多个结果部分，至少一个输入部分包括多个数据值 ; 并且对于包括多个数据值的输入部分中的至少一个，对该输入部分内的数据值执行独立的交换操作以形成结果数据字Rd，其中相应的结果部分的数据值相对于那个输入部分。这提供了一种特别有效的技术，用于在支持各种数据结构的数据处理设备中提供端到端反转功能，例如打包半字，零扩展半字，扩展符号等。

2. 发明授权

US5426448A Pixel display palette 失效
标题翻译：像素显示调色板
公开(公告)号：US5426448A
公开(公告)日：1995-06-20
申请号：US168774
申请日：1993-12-15
申请人： David J. Seal
发明人： David J. Seal
IPC分类号： G09G5/06 , H04N9/74
CPC分类号： G09G5/06
摘要： An apparatus for mapping a logical pixel value 2 defining pixel appearance to a plurality of physical appearance component values for driving a display device is described. Read addresses for a plurality of palettes 4, 6, 8 and 10 are derived from bits of the logical pixel value. The portions of the logical pixel value which are used to provide these read addresses overlap. Multiple storage of given physical appearance values GPV0, GPV1, . . . within the palettes is provided so as to ensure the appropriate output irrespective of what particular value a bit has that is non-significant for that palette. Three component color palettes 4, 6 and 8 addressed with 8-bit addresses are provided together with an effects palette 10 addressed by a 4-bit address. In the case of a 16-bit logical pixel value, the system has the flexibility to support any of 6-5-5, 5-6-5 or 5-5-6 depending upon what is stored within the color palettes.
摘要翻译：描述用于将限定像素外观的逻辑像素值2映射到用于驱动显示装置的多个物理外观分量值的装置。从逻辑像素值的位导出多个调色板4,6,8和10的读地址。用于提供这些读取地址的逻辑像素值的部分重叠。给定物理外观值的多重存储GPV0，GPV1，。。。提供调色板内的，以便确保适当的输出，而不管具有哪一特定值对于该调色板而言不重要。与由8位地址寻址的三组分调色板4,6和8一起提供了由4位地址寻址的效果调色板10。在16位逻辑像素值的情况下，系统可以灵活地支持6-5-5,5-6-5或5-5-6中的任何一种，具体取决于调色板中存储的内容。

3. 发明授权

US06170001A System for transfering format data from format register to memory wherein format data indicating the distribution of single or double precision data type in the register bank 失效
标题翻译：用于将格式数据从格式寄存器传送到存储器的系统，其中格式数据指示单个或双精度数据类型在寄存器组中的分布
公开(公告)号：US06170001A
公开(公告)日：2001-01-02
申请号：US09085756
申请日：1998-05-27
申请人： Christopher N. Hinds , David J. Seal
发明人： Christopher N. Hinds , David J. Seal
IPC分类号： G06F738
CPC分类号： G06F9/3822 , G06F9/30036 , G06F9/30043 , G06F9/30112 , G06F9/3012 , G06F9/30181 , G06F9/30185 , G06F9/30189 , G06F9/3877 , Y10S707/99936
摘要： A data processing apparatus and method is provided, wherein in a first mode of operation, data of a first data type is processed, and in a second mode of operation, data of a second data type consisting of an even multiple of data words is processed. The data processing apparatus comprises a register bank having a plurality of data slots for storing data words of data of said first type data and data words of data of said second type data, and transfer logic, responsive to a store instruction, to control the storing of the data words in the register bank to a memory. Further, a format register is provided for storing format data indicating the distribution in the register bank of data words of data of said first data type and data words of data of said second data type. In said second mode, the transfer logic is responsive to said store instruction specifying an even number of data words to cause those data words to be stored from said register bank to said memory, and is responsive to said store instruction specifying an odd number of data words, to cause the format data from the format register to be stored to said memory along with an even number of data words from the register bank. Hence, in situations where the data in the register bank needs to be temporarily stored to memory for subsequent retrieval into the register bank, all that is required is for the store instruction to be issued in said second mode specifying an odd number of data words, and this will automatically cause the contents of the format register to be stored to memory in addition to the required even number of data words from the register bank.
摘要翻译：提供了一种数据处理装置和方法，其中在第一操作模式中处理第一数据类型的数据，并且在第二操作模式中，处理由数据字的偶数倍组成的第二数据类型的数据。所述数据处理装置包括具有多个数据时隙的寄存器组，所述数据时隙用于存储所述第一类型数据的数据的数据字和所述第二类型数据的数据的数据字，以及响应于存储指令的传输逻辑，以控制存储的寄存器组中的数据字到存储器。此外，提供格式寄存器，用于存储指示在所述寄存器组中分配所述第一数据类型的数据的数据字和所述第二数据类型的数据的数据字的格式数据。在所述第二模式中，所述传送逻辑响应所述存储指令，指定偶数个数据字，以使所述数据字从所述寄存器组存储到所述存储器，并且响应所述存储指令指定奇数数据字，使来自格式寄存器的格式数据与来自寄存器组的偶数个数据字一起存储到所述存储器中。因此，在寄存器组中的数据需要临时存储到存储器以用于随后的情况下检索到寄存器组中，所需要的是用于以指定奇数数据字的所述第二模式发出存储指令，并且这将自动使格式化寄存器的内容除了需要来自注册银行的偶数数据字。

4. 发明授权

US5583804A Data processing using multiply-accumulate instructions 失效
标题翻译：使用多重累加指令进行数据处理
公开(公告)号：US5583804A
公开(公告)日：1996-12-10
申请号：US379014
申请日：1995-01-27
申请人： David J. Seal , Guy Larri , David V. Jaggar
发明人： David J. Seal , Guy Larri , David V. Jaggar
IPC分类号： G06F7/52 , G06F7/523 , G06F7/527 , G06F7/544 , G06F9/302 , G06F9/305 , G06F17/10 , G06F7/38
CPC分类号： G06F7/5443 , G06F9/30014
摘要： A data processing system is described utilizes a multiplier-accumulator 108 that performs both a first class of multiply-accumulate instructions and a second class of multiply-accumulate instructions. The first class of multiply-accumulate instructions are of the form N*N+N.fwdarw.N and the second class of multiply-accumulate instructions are of the form N*N+2N.fwdarw.2N. The second class of multiply-accumulate instructions provide a greater precision of arithmetic in a single instruction and avoid the use of excessive instruction set space by being constrained that the result is written back into the two registers from which the 2N-bit accumulate value was taken. The multiplier-accumulator also provides N*N.fwdarw.N and N*N.fwdarw.2N multiplication operations.
摘要翻译：描述了一种数据处理系统，其利用执行第一类乘法累加指令和第二类乘法累加指令的乘法器 - 累加器108。第一类乘法累加指令的格式为N * N + N> N，第二类乘法累加指令的格式为N * N + 2N-> 2N。第二类乘法累加指令在单个指令中提供更高的算术精度，并避免使用过多的指令集空间来限制结果被写回到采用2N位累加值的两个寄存器中。乘法器累加器还提供N * N> N和N * N> 2N乘法运算。

5. 发明授权

US5528529A Electronic multiplying and adding apparatus and method 失效
标题翻译：电子倍增装置及方法
公开(公告)号：US5528529A
公开(公告)日：1996-06-18
申请号：US303663
申请日：1994-09-09
申请人： David J. Seal
发明人： David J. Seal
IPC分类号： G06F7/53 , G06F7/533 , G06F7/544 , G06F17/10 , H03H17/02 , G06F7/52
CPC分类号： G06F7/5443
摘要： A multiply-accumulate circuit is described in which upon each multiply iteration some of the accumulate value bits are incorporated into the result with lower order subsequently non-changing bits being latched. In this way, a wide accumulate value can be dealt with without incurring a correspondingly wide data path through the multiply accumulate circuit. Initialisation of the multiply accumulate circuit with one of the carry value and save value as the first partial summand and the other as at least part of the accumulate value is performed to reduce the total number of iterative cycles required to produce the result.
摘要翻译：描述了一种乘法累加电路，其中在每次乘法迭代时，一些累加值比特被并入结果，其中较低级的随后不变位被锁存。以这种方式，可以处理广泛的累加值，而不会产生通过乘法累加电路的相应宽的数据路径。执行具有作为第一部分加法器的进位值和保存值之一的乘法累加电路作为累加值的至少一部分的初始化，以减少产生结果所需的迭代循环的总数。

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