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1. 发明授权

US08082589B2 Diagnostic data capture control for multi-domain processors 有权
标题翻译：多域处理器的诊断数据捕获控制
公开(公告)号：US08082589B2
公开(公告)日：2011-12-20
申请号：US10714178
申请日：2003-11-17
申请人： Luc Orion , David Hennah Mansell
发明人： Luc Orion , David Hennah Mansell
IPC分类号： H04N7/16
CPC分类号： G06F21/71 , G06F2221/2105
摘要： There is provided a processor operable in a first domain and a second domain, the processor comprising: monitoring logic operable to monitor the processor and capture diagnostic data; a storage element operable to contain at least one control parameter; control logic operable to control the monitoring logic in dependence on the at least one control parameter and the domain in which the processor is operating, to suppress capturing of diagnostic data relating to predetermined activities of the processor in the first domain. In some embodiments the first domain is a secure domain and the second domain is a non-secure domain, the monitoring function being debug or trace.
摘要翻译：提供了可在第一域和第二域中操作的处理器，所述处理器包括：监视逻辑，可操作以监视处理器并捕获诊断数据; 存储元件，其可操作以包含至少一个控制参数; 控制逻辑可操作以根据所述至少一个控制参数和所述处理器在其中操作的所述域来控制所述监视逻辑，以抑制与所述第一域中的所述处理器的预定活动有关的诊断数据的捕获。在一些实施例中，第一域是安全域，而第二域是非安全域，监视功能是调试或跟踪。

2. 发明申请

US20100235579A1 Cache Management Within A Data Processing Apparatus 有权
标题翻译：数据处理装置内的缓存管理
公开(公告)号：US20100235579A1
公开(公告)日：2010-09-16
申请号：US12223173
申请日：2006-09-18
申请人： Stuart David Biles , Richard Roy Grisenthwaite , David Hennah Mansell
发明人： Stuart David Biles , Richard Roy Grisenthwaite , David Hennah Mansell
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/127 , G06F12/0862
摘要： A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache. It has been found that such an approach provides a very flexible technique for seeking to improve cache storage utilisation.
摘要翻译：提供了一种数据处理装置以及管理这种装置中的至少一个高速缓存的方法。数据处理装置具有用于执行指令序列的至少一个处理单元，每个这样的处理单元具有与其相关联的高速缓冲存储器，每个高速缓冲存储器具有多个高速缓存行，用于存储由相关联的处理单元执行访问时的数据值指令序列提供了识别逻辑，对于每个高速缓存来说，监视数据处理装置内的数据业务，并且基于此，生成用于驱逐的标识的优选，以便识别为驱逐优选的一个或多个数据值。然后，对于每个高速缓存，缓存维护逻辑被设置为实现高速缓存维护操作，在该高速缓存维护操作期间，考虑到存储的数据值的识别逻辑生成的用于逐出识别的任何优选的执行，从该高速缓存中选择一个或多个数据值在那个缓存中。已经发现，这种方法为寻求提高缓存存储利用率提供了非常灵活的技术。

3. 发明申请

US20090222816A1 Data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuirty 有权
标题翻译：用于通过处理循环执行的虚拟机来控制对安全存储器的访问的数据处理装置和方法
公开(公告)号：US20090222816A1
公开(公告)日：2009-09-03
申请号：US12379082
申请日：2009-02-12
申请人： David Hennah Mansell , Richard Roy Grisenthwaite , Stuart David Biles
发明人： David Hennah Mansell , Richard Roy Grisenthwaite , Stuart David Biles
IPC分类号： G06F9/455
CPC分类号： G06F12/145
摘要： A data processing apparatus and method are provided for controlling access to secure memory by virtual machines executing on processing circuitry. The processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system is provided for storing data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address. A trusted virtual machine identifier is maintained and managed by the hypervisor software, with the hypervisor software setting the trusted virtual machine identifier if the current virtual machine is to be trusted to access the secure memory. Accordingly, in response to the access request issued by the current virtual machine, the address translation circuitry is only able to cause the modified access request to be issued as a secure access request specifying a physical address within the secure memory if the trusted virtual machine identifier is set. By such an approach, the hypervisor software is able to support multiple virtual machines at least some of which have access to secure memory under conditions controlled by the hypervisor software.
摘要翻译：提供了一种数据处理装置和方法，用于通过在处理电路上执行的虚拟机来控制对安全存储器的访问。处理电路执行管理程序软件以支持处理电路上的多个虚拟机的执行。提供了一种用于存储由处理电路进行访问的数据的存储器系统，该存储器系统包括用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器，该安全存储器仅可通过安全访问请求访问。地址转换电路响应于指定虚拟地址的当前虚拟机发出的访问请求，执行地址转换处理以识别存储器中的物理地址，并且将经修改的访问请求发布到存储器系统指定物理地址。由管理程序软件维护和管理可信赖的虚拟机标识符，如果当前虚拟机被信任以访问安全存储器，则管理程序软件设置可信虚拟机标识符。因此，响应于当前虚拟机发出的访问请求，地址转换电路仅能够将修改的访问请求作为指定安全存储器内的物理地址的安全访问请求发出，如果可信虚拟机标识符被设置。通过这种方法，管理程序软件能够支持多个虚拟机，其中至少一些虚拟机在由管理程序软件控制的条件下可以访问安全存储器。

4. 发明申请

US20070143515A1 Interrupt controller utilising programmable priority values 有权
标题翻译：中断控制器利用可编程优先级值
公开(公告)号：US20070143515A1
公开(公告)日：2007-06-21
申请号：US11603091
申请日：2006-11-22
申请人： Daniel Kershaw , Richard Roy Grisenthwaite , Stuart David Biles , David Hennah Mansell
发明人： Daniel Kershaw , Richard Roy Grisenthwaite , Stuart David Biles , David Hennah Mansell
IPC分类号： G06F13/26
CPC分类号： G06F21/52 , G06F13/26
摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.
摘要翻译：中断控制器2设置有优先级寄存器6，优先级寄存器6存储优先级值P 0 -P 9，用于确定接收到的中断信号I 0至I 9之间的优先级。优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

5. 发明授权

US08051271B2 Translation of virtual to physical addresses 有权
标题翻译：虚拟到物理地址的翻译
公开(公告)号：US08051271B2
公开(公告)日：2011-11-01
申请号：US12216253
申请日：2008-07-01
申请人： Jeremy Piers Davies , David Hennah Mansell , Richard Roy Grisenthwaite
发明人： Jeremy Piers Davies , David Hennah Mansell , Richard Roy Grisenthwaite
IPC分类号： G06F12/02
CPC分类号： G06F12/126 , G06F12/1036
摘要： Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries.
摘要翻译：公开了用于将数据处理器的虚拟地址转换为物理地址的地址转换电路，以响应来自所述数据处理器的虚拟地址的访问请求。地址转换电路包括：数据存储器，包括多个条目，用于存储虚拟地址范围的多个映射到所述数据处理器的物理地址范围和与表内的所述多个映射中的每一个相关联的附加数据; 更新电路，用于响应于未被所述表映射的虚拟地址的访问请求来更新所述表，所述更新电路响应于接收到所述虚拟地址的映射，以选择在所述表中适合的多个条目存储所述接收的映射; 并且根据存储在所述多个选择的条目中的所述一个中的所述附加数据的至少一部分，确定要被所述接收的映射覆盖的所述多个所选择的条目中的一个。

6. 发明申请

US20090320048A1 TASK FOLLOWING BETWEEN MULTIPLE OPERATING SYSTEMS 有权
标题翻译：在多个操作系统之间的任务
公开(公告)号：US20090320048A1
公开(公告)日：2009-12-24
申请号：US10714482
申请日：2003-11-17
申请人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Dominic Hugo Symes
发明人： Simon Charles Watt , Christopher Bentley Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Eric Sebastien Brochier , David Hennah Mansell , Dominic Hugo Symes
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/4812 , G06F9/526
摘要： A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
摘要翻译：处理器可以利用两个可以进行呼叫的操作系统（非安全的，安全的）。为了使第二操作系统能够跟踪由第一操作系统进行的任务切换，每次对第二操作系统进行呼叫时，该呼叫包括标识符，以便能够在第一操作系统上执行的任务之间进行区分，那个电话是做的。标识符可以是呼叫标识符和/或目标线程标识符，并且可以包括其他参数。

7. 发明申请

US20090177830A1 Handling interrupts in data processing 有权
标题翻译：处理数据处理中断
公开(公告)号：US20090177830A1
公开(公告)日：2009-07-09
申请号：US12379970
申请日：2009-03-05
申请人： Luc Orion , David Hennah Mansell , Michael Robert Nonweiler
发明人： Luc Orion , David Hennah Mansell , Michael Robert Nonweiler
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/3636 , G06F11/3656 , G06F11/3664
摘要： A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.
摘要翻译：一种处理数据的方法，包括：使用可执行多个功能的处理器处理功能，所述处理器具有使能的中断; 在处理器处接收中断; 暂停处理功能; 访问至少一个控制参数，所述至少一个控制参数指示是否应该从其被中断的点恢复该功能的处理，或者该中断之后应该重复该功能; 在完成功能开始的中断继续处理之后，或者根据控制参数中断处理中断点。作为应用程序，线程，系统软件程序或由软件定义的多个处理步骤的功能。

8. 发明授权

US07171539B2 Apparatus and method for controlling access to a memory 有权
公开(公告)号：US07171539B2
公开(公告)日：2007-01-30
申请号：US10713454
申请日：2003-11-17
申请人： David Hennah Mansell , Michael Robert Nonweiler , Peter Guy Middleton
发明人： David Hennah Mansell , Michael Robert Nonweiler , Peter Guy Middleton
IPC分类号： G06F12/14
CPC分类号： G06F12/1491 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/145
摘要： The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required. At least one memory management unit is provided which is operable, upon receipt of the memory access request from the processor, to perform conversion of a virtual address specified by the memory access request to a physical address. A first set of tables is provided, each table in the first set containing a number of first descriptors, each first descriptor containing at least a virtual address portion and a corresponding intermediate address portion, and a second set of tables is also provided, with each table in the second set containing a number of second descriptors, each second descriptor containing at least an intermediate address portion and a corresponding physical address portion. The second set of tables are managed by the processor when operating in a privileged mode which is not a non-secure mode, and hence remains secure. The at least one memory management unit is then operable to cause predetermined tables in the first and second set to be referenced to enable the conversion of the virtual address specified by the memory access request to a physical address.

9. 发明授权

US07146491B2 Apparatus and method for generating constant values 有权
标题翻译：用于产生常数值的装置和方法
公开(公告)号：US07146491B2
公开(公告)日：2006-12-05
申请号：US10972769
申请日：2004-10-26
申请人： Jonathan Sean Callan , David Hennah Mansell , Christopher Pedley , David James Seal
发明人： Jonathan Sean Callan , David Hennah Mansell , Christopher Pedley , David James Seal
IPC分类号： G06F9/302 , G06F9/315
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/30167
摘要： A data processing apparatus and method for generating constant values is provided. The data processing apparatus comprises a data processing unit operable in response to an instruction to perform a data processing operation on one or more data values. Shift logic is operable to selectively apply a shift operation to data to produce one of the data values for the data processing operation. Further, a plurality of registers are provided for storing data. The instruction has a register specifier field for identifying a register and a shift specifier field for specifying a shift to be applied to that register's data in order to produce one of the data values for the data processing operation. The register specifier field is allocatable a distinguished value, and if the register specifier field has that distinguished value, the shift logic is provided with a predetermined value and generates therefrom one of a plurality of constant values dependent on the shift specified by the shift specifier field, the generated constant value then being used as one of the data values for the data processing operation.
摘要翻译：提供了一种用于产生常数值的数据处理装置和方法。数据处理装置包括数据处理单元，该数据处理单元响应于对一个或多个数据值执行数据处理操作的指令而可操作。移位逻辑可操作以选择性地对数据应用移位操作以产生用于数据处理操作的数据值之一。此外，提供多个用于存储数据的寄存器。指令具有用于识别寄存器的寄存器说明符字段和用于指定要应用于该寄存器的数据的移位的移位说明符字段，以便产生数据处理操作的数据值之一。寄存器说明符字段是可分配的识别值，并且如果寄存器说明符字段具有该识别值，则向移位逻辑提供预定值，并由此产生取决于由移位说明符字段指定的移位的多个常数值之一，然后将所生成的常数值用作数据处理操作的数据值之一。

10. 发明授权

US08578136B2 Apparatus and method for mapping architectural registers to physical registers 有权
标题翻译：将架构寄存器映射到物理寄存器的装置和方法
公开(公告)号：US08578136B2
公开(公告)日：2013-11-05
申请号：US12801576
申请日：2010-06-15
申请人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Luca Scalabrino , Richard Roy Grisenthwaite , David Hennah Mansell
发明人： Frederic Claude Marie Piry , Louis-Marie Vincent Mouton , Luca Scalabrino , Richard Roy Grisenthwaite , David Hennah Mansell
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/384 , G06F9/3861 , G06F9/45558
摘要： An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The available register identifying circuitry is arranged to reference the configuration storage, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers. This enables the performance benefits from performing register renaming to be improved, without the need to increase the number of physical registers within the physical register set.
摘要翻译：提供了一种用于执行寄存器重命名的装置和方法，其中来自一组架构寄存器的架构寄存器从一组物理寄存器映射到物理寄存器。提供了可用的寄存器识别电路，其响应于设备的当前状态，以识别哪些物理寄存器形成可被寄存器重命名电路映射到可由要执行的指令指定的架构寄存器的物理寄存器池。配置存储器存储其值在处理电路的操作期间被修改的配置数据，使得当配置数据具有第一值时，配置数据标识架构寄存器集的至少一个体系结构寄存器，其不需要映射到物理寄存器通过寄存器重命名电路。可用的寄存器识别电路被布置为引用配置存储器，使得当配置数据具有第一值时，由于需要映射到物理寄存器的架构寄存器的数量的减少，池中的物理寄存器的数量增加。这使得能够改进执行寄存器重命名的性能优势，而不需要增加物理寄存器集中的物理寄存器的数量。

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