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    • 1. 发明申请
    • Method and Apparatus to Monitor Circuit Variation Effects on Electrically Programmable Fuses
    • 监测电路可编程保险丝的电路变化影响的方法和装置
    • US20080158933A1
    • 2008-07-03
    • US11619287
    • 2007-01-03
    • David H. AllenPhil C. F. PaoneGregory J. Uhlmann
    • David H. AllenPhil C. F. PaoneGregory J. Uhlmann
    • G11C17/16G11C17/00
    • G11C17/18
    • A monitor bank consists of test one time programmable memory that is programmed distinctively from functional one time programmable memory in order to determine whether the functional one time programmable memory has or will program successfully. In a specific embodiment, each monitor bank consists of a first eFuse configured to expectedly never blow, a second eFuse configured to expectedly always blow, and at least a third eFuse configured to be more difficult to blow than the first eFuse, but easier to blow than the second eFuse. The method of determining whether functional eFuses have or will be programmed successfully is described: programming a monitor bank; sensing whether the test eFuses have blown; creating a monitor bank bit line blow pattern; determining an anticipated bit line blow pattern; comparing the two patterns; and determining that the functional eFuses will not blow successfully if the patterns do not match.
    • 监视器组包括测试一次可编程存储器,其与功能一次可编程存储器区分开来,以确定功能一次可编程存储器是否具有或将成功编程。 在具体实施例中,每个监视器组包括被配置为预期不会吹动的第一eFuse,被配置为预期总是吹动的第二eFuse,以及被配置为比第一eFuse更难吹击的至少第三eFuse,但是更容易吹 比第二个eFuse。 描述了确定功能性eFuse是否具有或将被编程成功的方法:编程监视器组; 感测测试eFuses是否已经被吹; 创建监控银行位线打击模式; 确定预期的位线打击模式; 比较两种模式; 并且如果模式不匹配,则确定功能eFuses不会成功地吹奏。
    • 3. 发明授权
    • Method and apparatus for safe mode in dynamic logic using dram cell
    • 方法和装置在动态逻辑中使用电容器的安全模式
    • US5910735A
    • 1999-06-08
    • US861586
    • 1997-05-22
    • David H. Allen
    • David H. Allen
    • H03K19/096
    • H03K19/0963
    • A dynamic logic circuit operates in a normal mode, and in a safe mode for which the circuit is less susceptible to noise than with the normal mode. The dynamic logic circuit includes a logic network having at least one input, a precharge device having a storage node connected to the logic network, and a device for varying a capacitance of the storage node to provide the normal and safe modes of operation. In one embodiment, the capacitance at the storage node is varied by selectively connecting the storage node to a capacitor, particularly to a DRAM cell capacitor. The DRAM cell is advantageously fabricated on a chip in close proximity to the storage node. A logic process using a plurality of such dynamic logic circuits can have means for independently operating each of the circuits in the safe mode, and the circuits can be monitored during the normal and safe operation modes to determine whether any are failing during the normal operation mode, e.g., due to excess noise.
    • 动态逻辑电路在正常模式下运行,并且在电路比正常模式下更不易受噪声影响的安全模式下工作。 动态逻辑电路包括具有至少一个输入的逻辑网络,具有连接到逻辑网络的存储节点的预充电装置,以及用于改变存储节点的电容以提供正常和安全操作模式的装置。 在一个实施例中,通过选择性地将存储节点连接到电容器,特别是DRAM单元电容器来改变存储节点处的电容。 有利地,在靠近存储节点的芯片上制造DRAM单元。 使用多个这样的动态逻辑电路的逻辑处理可以具有用于在安全模式下独立地操作每个电路的装置,并且可以在正常和安全操作模式期间监视电路,以确定在正常操作模式期间是否有故障 ,例如由于噪音过大。
    • 7. 发明授权
    • Data communication method using identification protocol
    • 数据通信方法采用识别协议
    • US5627544A
    • 1997-05-06
    • US619274
    • 1996-03-18
    • Charles K. SnodgrassDavid H. AllenJohn R. TuttleRobert R. RotzollGeorge E. Pax
    • Charles K. SnodgrassDavid H. AllenJohn R. TuttleRobert R. RotzollGeorge E. Pax
    • G01S13/75G01S13/76G01S13/78G06K19/07G06K19/073H04L29/12
    • H04L29/12254G01S13/758G01S13/765G06K19/0723G06K19/073G06K7/10019H04L29/12264H04L29/12292H04L29/12311H04L29/1232H04L29/12783H04L29/12801H04L29/12839H04L61/2038H04L61/2046H04L61/2069H04L61/2084H04L61/2092H04L61/35H04L61/6004H04L61/6022G01S13/78
    • A protocol is used to coordinate the use of a common communication medium by one or more interrogating commander stations and an unknown plurality of responding responder stations. Each commander station and each responder station is equipped to broadcast messages and to check for error in received messages. When more than one station attempts to broadcast simultaneously, an erroneous message is received and communication is interrupted. To establish uninterrupted communication, a commander station broadcasts a command causing each responder station of a potentially large first number of responder stations to each select a random number from a known range and retain it as its arbitration number. After receipt of such a command, each addressed responder station transmits a response message containing its arbitration number. Zero, one, or several responses may occur simultaneously. By broadcasting requests for identification to various subsets of the full range of arbitration numbers and checking for an immediate error-free response, a commander station can determine the arbitration number of every responder station capable of communicating at the time. Consequently, a commander station can conduct subsequent uninterrupted communication with each responder station, for example by addressing only one responder station. Responder stations of this invention require minimal logic and circuitry to respond to multiple commander stations.
    • 协议用于协调由一个或多个询问指挥员站和未知的多个响应响应站的公共通信介质的使用。 每个指挥台和每个响应站都配备了广播消息并检查收到的消息中的错误。 当多个站尝试同时广播时,接收到错误的消息并中断通信。 为了建立不间断的通信,指挥台广播一个命令,使每个响应者站的潜在的大的第一个响应站的每一个都从一个已知的范围中选出一个随机数,并将其保留为其仲裁号。 在接收到这样的命令之后,每个寻址响应站发送包含其仲裁号的响应消息。 零,一个或几个响应可能同时发生。 通过向全方位仲裁号码的各种子集广播识别请求,并立即检查无误差的响应,指挥台可以确定当时能够进行通信的每个响应者站的仲裁号码。 因此,指挥台可以进行与每个应答者站的后续的不间断的通信,例如通过仅寻址一个应答站。 本发明的响应站要求最小的逻辑和电路来响应多个指挥台。
    • 10. 发明授权
    • Power supply current spike reduction techniques for an integrated circuit
    • 用于集成电路的电源电流尖峰抑制技术
    • US07954000B2
    • 2011-05-31
    • US12013928
    • 2008-01-14
    • David H. AllenRoger J. GravrokKenneth A. Van Goor
    • David H. AllenRoger J. GravrokKenneth A. Van Goor
    • G06F1/08
    • G06F1/10
    • An integrated circuit includes a first clock island, a second clock island, a clock generator, and a first programmable delay element. The first clock island is configured to receive a first clock signal. The second clock island is configured to receive a second clock signal. The clock generator is configured to provide a generated clock signal and the first and second clock signals are based on the generated clock signal. The first programmable delay element is coupled between the clock generator and the first clock island. The first programmable delay element is configured to receive the generated clock signal and provide the first clock signal. The integrated circuit is configured to account for a clock skew between the first and second clock signals when information is transferred between the first and second clock islands. In this manner, a predetermined amount of the clock skew may be introduced between the first and second clock signals to smear out, over time, instantaneous power supply current demands of respective logic within the first and second clock islands.
    • 集成电路包括第一时钟岛,第二时钟岛,时钟发生器和第一可编程延迟元件。 第一时钟岛被配置为接收第一时钟信号。 第二时钟岛被配置为接收第二时钟信号。 时钟发生器被配置为提供生成的时钟信号,并且第一和第二时钟信号基于所生成的时钟信号。 第一可编程延迟元件耦合在时钟发生器和第一时钟岛之间。 第一可编程延迟元件被配置为接收生成的时钟信号并提供第一时钟信号。 当信息在第一和第二时钟岛之间传送时,集成电路被配置为考虑第一和第二时钟信号之间的时钟偏移。 以这种方式,可以在第一和第二时钟信号之间引入预定量的时钟偏差,以随着时间推移在第一和第二时钟岛内的相应逻辑的瞬时电源电流需求。