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    • 3. 发明授权
    • Self-aligned contact formation for semiconductor devices
    • 用于半导体器件的自对准接触形成
    • US06207571B1
    • 2001-03-27
    • US09515804
    • 2000-02-29
    • Werner JuenglingKirk PrallTrung T. DoanGuy T. BlalockDavid DickersonDavid S. Becker
    • Werner JuenglingKirk PrallTrung T. DoanGuy T. BlalockDavid DickersonDavid S. Becker
    • H01L2100
    • H01L27/10894H01L21/316H01L21/31625H01L21/76897
    • In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.
    • 根据本发明,提供了一种用于在诸如DRAM的集成电路上制造接触的方法。 该方法包括以下步骤。 在集成电路上形成栅极堆叠。 在栅叠层的侧壁上形成间隔物。 在集成电路上形成绝缘膜。 绝缘膜平坦化。 最后,通过平坦化绝缘膜形成栅极接触开口。 在一个实施例中,通过蚀刻去除绝缘体,间隔物和绝缘膜来形成栅极接触开口。 在该实施例中,以基本相似的速率蚀刻绝缘体,间隔物和绝缘膜。 因此,集成电路容忍掩模未对准,并且不会过度蚀刻场氧化物或产生氮化硅条。 在另一个实施例中,平面化步骤通过化学机械平面化进行,以在集成电路的表面上形成基本平坦的形貌。 因此,本发明不需要具有相当大的深度场的光刻设备。 在第三个实施例中,该方法可以包括额外的步骤,包括在集成电路上形成附加电介质。 然后,通过附加电介质形成栅极和位线接触开口。 最后,栅极和位线触点形成为与栅极堆叠自对准。 该实施例可以通过用蚀刻去除附加电介质但不基本上去除间隔物的栅极和位线接触开口来实现。 因此,位线接触不能无意中连接到用作字线的栅极堆叠。 此连接可能会禁用集成电路。