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1. 发明授权

US07000204B2 Power estimation based on power characterizations 有权
标题翻译：基于功率特征的功率估计
公开(公告)号：US07000204B2
公开(公告)日：2006-02-14
申请号：US10653650
申请日：2003-09-02
申请人： Tyson R. McGuffin , Thomas W. Chen , David C. Burden
发明人： Tyson R. McGuffin , Thomas W. Chen , David C. Burden
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations associated with dynamic and static power related parameters of a circuit design. The power characterizations can be determined prior to circuit design optimizations, stored and utilized during circuit design optimizations.
摘要翻译：提供了可用于估计与电路设计相关联的功率的系统和方法。通过使用与电路设计的动态和静态功率相关参数相关联的功率特征来确定估计功率。功率特征可以在电路设计优化之前确定，在电路设计优化期间存储和利用。

2. 发明授权

US06892374B2 Systems and methods for generating an artwork representation according to a circuit fabrication process 有权
标题翻译：根据电路制作工艺生成艺术作品表示的系统和方法
公开(公告)号：US06892374B2
公开(公告)日：2005-05-10
申请号：US10174674
申请日：2002-06-19
申请人： Bruno P. Melli , David C. Burden , Matthew L. Biggio
发明人： Bruno P. Melli , David C. Burden , Matthew L. Biggio
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： In one embodiment, the present invention relates to a system for generating an artwork representation according to a circuit fabrication process. The system comprises a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of the plurality of circuit cells is defined by a sub-mask for a respective logical device according to the circuit fabrication process; an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and the cell library; and an artwork generator that generates an artwork representation that defines a mask for etching of the generated circuit layout according to the circuit fabrication process.
摘要翻译：在一个实施例中，本发明涉及一种用于根据电路制造过程生成图形表示的系统。该系统包括存储至少与多个电路单元相关联的尺寸信息的单元库，其中多个电路单元中的每一个由根据电路制造工艺的相应逻辑器件的子掩模定义; 实例布置引擎，其生成由至少指定逻辑设备和单元库的布置的规范文件定义的电路布局; 以及艺术品生成器，其生成根据电路制造工艺定义用于蚀刻所生成的电路布局的掩模的艺术品表示。

3. 发明授权

US06691285B1 Exponential increments in FET size selection 失效
标题翻译： FET尺寸选择中的指数增量
公开(公告)号：US06691285B1
公开(公告)日：2004-02-10
申请号：US10229535
申请日：2002-08-27
申请人： David C. Burden , Dave Anderson
发明人： David C. Burden , Dave Anderson
IPC分类号： G06F1750
CPC分类号： G06F17/5063 , G06F17/505
摘要： A set of discrete transistor sizes spread in an exponential manner over a specified range is the basis for adjusted transistor sizes used to optimize a circuit. One of the discrete transistor sizes may be the original transistor size or other starting point for the optimization.
摘要翻译：在指定范围内以指数方式扩展的一组分立晶体管尺寸是用于优化电路的调整晶体管尺寸的基础。分立晶体管尺寸之一可以是原始晶体管尺寸或用于优化的其它起始点。

4. 发明授权

US06484301B1 System for and method of efficient contact pad identification 失效
标题翻译：高效接触垫识别系统和方法
公开(公告)号：US06484301B1
公开(公告)日：2002-11-19
申请号：US09865268
申请日：2001-05-25
申请人： David C Burden
发明人： David C Burden
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： The present invention includes a system for and a method of identifying the location of contact pads on interconnect layers of printed circuit boards or metal layers of integrated circuits. The invention groups the conductive surfaces into rectangular areas and applies a mask to the identified rectangular areas by aligning a corner of the mask with the corresponding corner of the rectangular area. Once aligned, the remaining corners of the mask are checked to see whether there is an underlying conductive material present at all corners thereby identifying a suitable location for a contact pad. The invention further includes an alignment of alternate corners of the mask with the corresponding corner of the rectangular area if previous attempts to identify a contact pad were unsuccessful.
摘要翻译：本发明包括用于识别印刷电路板或集成电路的金属层的互连层上的接触焊盘的位置的系统和方法。本发明将导电表面组合成矩形区域，并通过将掩模的角与矩形区域的相应角对齐，将掩模施加到所识别的矩形区域。一旦对准，检查掩模的其余角部以查看在所有拐角处是否存在下面的导电材料，从而识别接触焊盘的合适位置。本发明还包括如果先前尝试识别接触垫不成功，则将掩模的替代拐角与矩形区域的对应拐角对准。

5. 发明授权

US06862715B2 Systems and methods of cross-over current calculation within electronic designs 失效
标题翻译：电子设计中跨电流计算的系统和方法
公开(公告)号：US06862715B2
公开(公告)日：2005-03-01
申请号：US10207578
申请日：2002-07-29
申请人： David C. Burden , Matthew Biggi , Jaime Weisberg
发明人： David C. Burden , Matthew Biggi , Jaime Weisberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036 , G06F17/505
摘要： A process is shown for determining crossover current in a circuit design. One or more static CMOS gates are identified within the circuit design. One or more widths of at least one of a P-stack and N-stack associated with the CMOS gates are then determined. A voltage slope at the input of, and a capacitive load at the output of, one or more of the nodes are also determined. Crossover current, per static CMOS gate, is estimated based on the widths, the voltage slope and capacitive load. An overall crossover current is determined by summing individual gate-level crossover currents. The circuit design may be optimized for power consumption, for example, by modifying design elements of the circuit design while monitoring overall crossover current.
摘要翻译：示出了用于确定电路设计中的交叉电流的过程。在电路设计中识别出一个或多个静态CMOS门。然后确定与CMOS门相关联的P堆叠和N堆叠中的至少一个的一个或多个宽度。还确定了输入端的电压斜率和一个或多个节点的输出处的电容负载。根据宽度，电压斜率和容性负载来估计每个静态CMOS栅极的交叉电流。通过对各个门级交叉电流求和来确定整体交叉电流。电路设计可以针对功耗进行优化，例如，通过修改电路设计的设计元素，同时监视整体交叉电流。

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