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1. 发明授权

US08402409B1 Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit 有权
标题翻译：用于支持可编程逻辑集成电路中的运行时重新配置的方法和装置
公开(公告)号：US08402409B1
公开(公告)日：2013-03-19
申请号：US11373744
申请日：2006-03-10
申请人： Jorn W. Janneck , David B. Parlour , Paul R. Schumacher
发明人： Jorn W. Janneck , David B. Parlour , Paul R. Schumacher
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5054 , G06F8/30 , G06F15/7871
摘要： Method and apparatus for generating an implementation of a program language circuit description for a programmable logic device (PLD) is described. In one example, the program language circuit description is analyzed to identify constructs indicative of dynamic function re-assignment. A hardware description of the program language circuit description is generated. The hardware description includes a plurality of implementations responsive to the identified constructs. Physical implementation data is generated from the hardware description. The physical implementation includes a plurality of partial configurations for the PLD based on the respective plurality of implementations in the hardware description.
摘要翻译：描述了用于生成可编程逻辑器件（PLD）的程序语言电路描述的实现的方法和装置。在一个示例中，分析程序语言电路描述以识别指示动态功能重新分配的构造。生成程序语言电路描述的硬件描述。硬件描述包括响应于所识别的构造的多个实现。物理实现数据是从硬件描述生成的。物理实现包括基于硬件描述中的相应多个实现的PLD的多个部分配置。

2. 发明授权

US07380232B1 Method and apparatus for designing a system for implementation in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中设计用于实现的系统的方法和装置
公开(公告)号：US07380232B1
公开(公告)日：2008-05-27
申请号：US11373709
申请日：2006-03-10
申请人： Paul R. Schumacher , Jorn W. Janneck , David B. Parlour
发明人： Paul R. Schumacher , Jorn W. Janneck , David B. Parlour
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and apparatus for designing a system for implementation in a programmable logic device (PLD) is described. In one example, a program language description of the system is captured. The program language description includes control code for configuring actor elements with functions to perform tasks in response to input data. A hardware implementation is generated for the PLD from the program language description by mapping the control code to decision logic, the functions to partial configuration streams, and the actor elements to reconfigurable slots.
摘要翻译：描述了用于设计用于在可编程逻辑器件（PLD）中实现的系统的方法和装置。在一个示例中，捕获系统的程序语言描述。程序语言描述包括用于配置具有响应于输入数据执行任务的功能的actor元件的控制代码。通过将控制代码映射到决策逻辑，部分配置流的功能和可配置时隙的actor元素，从程序语言描述生成PLD的硬件实现。

3. 发明授权

US08595391B1 Automatic queue sizing for dataflow applications 有权
标题翻译：数据流应用程序的自动队列大小调整
公开(公告)号：US08595391B1
公开(公告)日：2013-11-26
申请号：US12048588
申请日：2008-03-14
申请人： Ian D. Miller , Jorn W. Janneck , David B. Parlour
发明人： Ian D. Miller , Jorn W. Janneck , David B. Parlour
IPC分类号： G06F5/00
CPC分类号： G06F17/5054
摘要： Automatic queue sizing for data flow applications for an integrated circuit is described. Queue sizes for queues of a dataflow network are initialized to a set of first sizes for running as distributed actors without having to have centralized control. If it is determined there is a deadlock, causes for the dataflow network being deadlocked are analyzed with a controller coupled thereto to select a first actor thereof. The first actor of the dataflow network is selected as being in a stalled write phase state. Queue size is incremented for at least one queue of the queues to unlock the first actor from the stalled write phase state. The running, the determining, the analyzing, and the incrementing are iteratively repeated to provide a second set of sizes for the queue sizes sufficient to reduce likelihood of deadlock of the data flow network.
摘要翻译：描述用于集成电路的数据流应用的自动队列大小。数据流网络队列的队列大小被初始化为一组第一个大小，用于作为分布式角色进行运行，而无需集中控制。如果确定存在死锁，则与其耦合的控制器分析数据流网络处于死锁状态的原因，以选择其第一actor。数据流网络的第一个演员选择为处于停止的写入阶段状态。对于至少一个队列队列，队列大小递增，以使第一个actor从停止的写入阶段状态解锁。迭代地重复运行，确定，分析和递增，以为足以减少数据流网络死锁可能性的队列大小提供第二组大小。

4. 发明授权

US08402164B1 Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit 有权
标题翻译：异步通信网络和在集成电路中实现数据异步通信的方法
公开(公告)号：US08402164B1
公开(公告)日：2013-03-19
申请号：US12913626
申请日：2010-10-27
申请人： David B. Parlour , Jorn W. Janneck , Ian D. Miller
发明人： David B. Parlour , Jorn W. Janneck , Ian D. Miller
IPC分类号： G06F15/16
CPC分类号： G06F15/163 , G06F15/7825 , G06F15/7867
摘要： An asynchronous communication network in an integrated circuit is described. The asynchronous communication network comprises a plurality of circuit elements enabling the transmission of tokens, each circuit element having a component interface comprising: a routing network coupled to a first adjacent circuit element of the plurality of circuit elements; and a control circuit coupled to the routing network, the control circuit having a first input coupled to receive a first command requesting a detection of a token received at a second input of the control circuit, and a first acknowledgement output coupling a first acknowledgement signal indicating whether the first command is received at the first input. Methods of enabling asynchronous communication in an integrated circuit are also disclosed.
摘要翻译：描述集成电路中的异步通信网络。异步通信网络包括能够传送令牌的多个电路元件，每个电路元件具有组件接口，包括：耦合到多个电路元件中的第一相邻电路元件的路由网络; 以及耦合到所述路由网络的控制电路，所述控制电路具有耦合以接收请求检测在所述控制电路的第二输入处接收到的令牌的第一命令的第一输入和耦合指示的第一确认信号的第一确认输出第一个命令是否在第一个输入接收。还公开了在集成电路中实现异步通信的方法。

5. 发明授权

US5367207A Structure and method for programming antifuses in an integrated circuit array 失效
标题翻译：用于在集成电路阵列中编程反熔丝的结构和方法
公开(公告)号：US5367207A
公开(公告)日：1994-11-22
申请号：US625732
申请日：1990-12-04
申请人： F. Erich Goetting , David B. Parlour , John E. Mahoney
发明人： F. Erich Goetting , David B. Parlour , John E. Mahoney
IPC分类号： G01R31/317 , G11C17/18 , H01L21/82 , H03K19/177 , H03K3/01 , H03K5/08 , H03K19/092
CPC分类号： G11C17/18
摘要： This invention provides a structure and method for interconnecting logic devices through line segments which can be joined by programming antifuses. One of several programming lines can be connected through an interconnect line segment to each terminal of each antifuse in the array. Interconnect line segments connected to opposite terminals of the same antifuse are connected to a different programming line in order to be able to apply different voltages to the two terminals of the antifuse. An addressing structure selectively connects interconnect line segments to their respective programming lines, and programming voltages applied to the programming lines cause a selected antifuse to be programmed. A novel addressing feature sequentially addresses two transistors for the line segments to be connected, and takes advantage of a capacitive pumped decoder to maintain the addressed transistors turned on while programming voltages are applied. The structure also allows for testing of logic devices by applying test voltages to the programming voltage lines and/or sensing logic device output on programming voltage lines. The structure and method also permit measuring resistance of the programmed antifuses. No separate testing overhead structure is needed.
摘要翻译：本发明提供了一种用于通过线段互连逻辑器件的结构和方法，其可以通过编程反熔丝来连接。几条编程线之一可以通过互连线段连接到阵列中每个反熔丝的每个端子。连接到相同反熔丝的相对端子的互连线段连接到不同的编程线，以便能够向反熔丝的两个端子施加不同的电压。寻址结构将互连线段选择性地连接到它们各自的编程线，并且施加到编程线的编程电压使得所选择的反熔丝被编程。一种新颖的寻址特征顺序地寻址要连接的线段的两个晶体管，并且利用电容性泵浦解码器来维持寻址晶体管在编程电压被施加时导通。该结构还允许通过对编程电压线上的编程电压线和/或感测逻辑器件输出施加测试电压来测试逻辑器件。该结构和方法还允许测量编程反熔丝的电阻。不需要单独的测试开销结构。

6. 发明授权

US08001510B1 Automated method of architecture mapping selection from constrained high level language description via element characterization 有权
标题翻译：通过元素表征从约束高级语言描述中的自动化体系结构映射方法选择
公开(公告)号：US08001510B1
公开(公告)日：2011-08-16
申请号：US12205825
申请日：2008-09-05
申请人： Ian D. Miller , Jorn W. Janneck , David B. Parlour , Paul R. Schumacher
发明人： Ian D. Miller , Jorn W. Janneck , David B. Parlour , Paul R. Schumacher
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosure is made of approaches for mapping an electronic design specification to an implementation. In one approach, quality metrics are associated with functional units of the design, and the functional units are mapped to respective initial implementations. For each functional unit a respective quality indicator is determined based on the mapping. The quality indicator specifies a degree to which the functional unit achieves the associated quality metric. At least one of the functional units is selected for remapping based on the quality indicator of that functional unit or the quality indicator of another functional unit. An alternative implementation to the initial implementation is selected for each selected functional unit to improve the quality indicator. The selected functional unit is remapped to the selected alternative implementation.
摘要翻译：披露了将电子设计规范映射到实现的方法。在一种方法中，质量度量与设计的功能单元相关联，并且功能单元被映射到相应的初始实现。对于每个功能单元，基于映射确定相应的质量指示符。质量指标指定功能单元实现相关质量度量的程度。基于该功能单元的质量指示符或另一功能单元的质量指示符，选择功能单元中的至少一个用于重新映射。为每个所选择的功能单元选择初始实现的替代实现以改善质量指标。所选择的功能单元被重新映射到所选择的替代实现。

7. 发明授权

US07437582B1 Power control in a data flow processing architecture 有权
标题翻译：数据流处理架构中的功率控制
公开(公告)号：US07437582B1
公开(公告)日：2008-10-14
申请号：US11200685
申请日：2005-08-10
申请人： David B. Parlour
发明人： David B. Parlour
IPC分类号： G06F1/10 , G06F1/26 , G06F1/32
CPC分类号： G06F1/12 , G06F1/26
摘要： Method and system for dynamically adjusting performance of circuitry blocks are described. A first circuit domain is coupled to an interim storage device. The first circuit domain includes a first level shifter coupled to an input of a first circuitry block and a second level shifter coupled to an output of the first circuitry block. The second level shifter is coupled between the output of the first circuitry block and an input of the interim storage device. A controller is coupled to the first circuit domain for adjustment of a first operating voltage of the first circuit domain.
摘要翻译：描述了用于动态调整电路块性能的方法和系统。第一电路域耦合到临时存储设备。第一电路域包括耦合到第一电路块的输入的第一电平移位器和耦合到第一电路块的输出的第二电平移位器。第二电平移位器耦合在第一电路块的输出和临时存储装置的输入之间。控制器耦合到第一电路域以调整第一电路域的第一工作电压。

8. 发明授权

US5867396A Method and apparatus for making incremental changes to an integrated circuit design 失效
标题翻译：用于对集成电路设计进行增量更改的方法和装置
公开(公告)号：US5867396A
公开(公告)日：1999-02-02
申请号：US523070
申请日：1995-08-31
申请人： David B. Parlour
发明人： David B. Parlour
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An incremental circuit design methodology using logic synthesis where comparisons are made between netlists corresponding to two separate versions of a design to determine similarities between the two. The similarities are then used to ensure the same physical implementation for the unchanged portion of the design. Therefore, information from the physical implementation of the previous design may be used in implementing the later design.
摘要翻译：使用逻辑综合的增量电路设计方法，其中对应于设计的两个单独版本的网表之间进行比较，以确定两者之间的相似性。然后使用相似之处来确保设计的不变部分具有相同的物理实现。因此，可以将以前设计的物理实现的信息用于实现后续设计。

9. 发明授权

US5574634A Regulator for pumped voltage generator 失效
标题翻译：泵浦电压调节器
公开(公告)号：US5574634A
公开(公告)日：1996-11-12
申请号：US176304
申请日：1994-01-03
申请人： David B. Parlour , Roger D. Carpenter
发明人： David B. Parlour , Roger D. Carpenter
IPC分类号： H02M3/07 , H02M3/18
CPC分类号： H02M3/073
摘要： According to the invention, a regulated voltage pump is provided which uses a chain of diodes between each of which is attached one plate of a capacitor for which the other plate is driven by a clock signal. The regulated voltage pump of the present invention uses feedback from the output signal to determine how many capacitors to pump. A comparator compares a signal related to the pumped output signal to a reference voltage (which may be the power supply voltage) and controls how many intermediate pumping capacitors receive a switching clock signal. Thus a regulated pumped voltage is provided.
摘要翻译：根据本发明，提供了一种调节电压泵，其使用二极管链，每个二极管连接在电容器的一个板上，另一个板由时钟信号驱动。本发明的调节电压泵使用来自输出信号的反馈来确定要泵送的电容器数量。比较器将与泵浦输出信号相关的信号与参考电压（可能是电源电压）进行比较，并控制多少中间泵浦电容接收开关时钟信号。因此提供了调节的泵浦电压。

10. 发明授权

US5349248A Adaptive programming method for antifuse technology 失效
标题翻译：反熔丝技术的自适应编程方法
公开(公告)号：US5349248A
公开(公告)日：1994-09-20
申请号：US940125
申请日：1992-09-03
申请人： David B. Parlour , F. Erich Goetting , Stephen M. Trimberger
发明人： David B. Parlour , F. Erich Goetting , Stephen M. Trimberger
IPC分类号： G11C17/16 , H03K19/177 , H01H37/76
CPC分类号： H03K19/17704 , G11C17/16
摘要： For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed. The method also includes swapping of logic cell inputs, logic cells, and/or logic blocks from their original layout to adapt to a failed antifuse without changing the timing of signals which would have used the failed antifuse.
摘要翻译：对于反熔丝可编程集成电路器件，特别是FPGA器件，本发明允许在不能编程的反熔丝周围的替代路由。芯片架构包括布线段和反熔丝，这些连接段和反熔丝一起允许在反熔丝发生故障的情况下围绕每个反熔丝的替代路线。该方法包括在计算机的控制下对设备进行编程，该计算机可以在无法编程的反熔丝的情况下重新计算路由。优选地，初始路由分配通过芯片的未使用的接线段以可用于围绕故障反熔丝进行布线。当发生故障时，该方法包括确定围绕每个故障反熔丝的替代路线。替代路线可以在反熔丝失败之后直接建立，或者在所有初始选择的反熔丝已被编程之后。该方法还包括从其原始布局交换逻辑单元输入，逻辑单元和/或逻辑块以适应故障反熔丝而不改变将使用故障反熔丝的信号的定时。

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