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1. 发明授权

US07592673B2 ESD protection circuit with isolated diode element and method thereof 有权
标题翻译：具有隔离二极管元件的ESD保护电路及其方法
公开(公告)号：US07592673B2
公开(公告)日：2009-09-22
申请号：US11692722
申请日：2007-03-28
申请人： David C. Burdeaux , Daniel J. Lamey
发明人： David C. Burdeaux , Daniel J. Lamey
IPC分类号： H01L23/62
CPC分类号： H01L27/0255 , H01L29/0692 , H01L29/16 , H01L29/6609 , H01L29/861
摘要： An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to −Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.
摘要翻译： ESD保护电路（20）包括ESD器件（24）和隔离二极管元件（30）。 ESD器件包括漏 - 源结隔离ESD晶体管（26,28）。隔离二极管元件与ESD器件串联耦合，并被配置为向需要ESD保护的晶体管器件（22）提供ESD保护。响应于保护晶体管器件的栅极上的-Vgs条件，串联耦合隔离二极管元件在隔离二极管元件的击穿状态之前防止ESD晶体管的漏 - 源结的正向偏置。此外，响应于足以导致对受保护的晶体管器件造成损害的ESD事件，串联耦合隔离二极管元件允许发生故障状态。此外，ESD保护电路可以在（i）受保护器件的正常工作的极性和（ii）除了受保护器件的正常操作之外的相反极性的情况下工作。

2. 发明授权

US07508021B2 RF power transistor device with high performance shunt capacitor and method thereof 有权
标题翻译：具有高性能并联电容器的RF功率晶体管器件及其方法
公开(公告)号：US07508021B2
公开(公告)日：2009-03-24
申请号：US11760775
申请日：2007-06-10
申请人： Xiaowei Ren , Daniel J. Lamey
发明人： Xiaowei Ren , Daniel J. Lamey
IPC分类号： H01L27/108
CPC分类号： H01L27/0629 , H01L23/5225 , H01L23/642 , H01L27/0207 , H01L28/40 , H01L28/60 , H01L29/41758 , H01L29/94 , H01L2223/6644 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated shunt capacitor comprises a bottom plate (86,88), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (62) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate (62); and a metallization feature (70) disposed about and isolated from at least two sides of the top plate (62), the metallization feature (70) for coupling the bottom plate (86,88) to the shield (74). In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.
摘要翻译：集成分流电容器包括底板（86,88），覆盖在底板的一部分上的电容器电介质（92），覆盖电容器电介质的顶板（62），覆盖顶部的一部分的屏蔽（74）板（62）; 以及金属化特征（70），其设置在所述顶板（62）的至少两侧周围并与所述顶板隔离，所述金属化特征（70）用于将所述底板（86,88）联接到所述屏蔽件（74）。在一个实施例中，RF功率晶体管具有包括本文所述的集成分流电容器的阻抗匹配网络。

3. 发明申请

US20070297120A1 RF POWER TRANSISTOR DEVICE WITH HIGH PERFORMANCE SHUNT CAPACITOR AND METHOD THEREOF 有权
标题翻译：具有高性能分流电容器的RF功率晶体管器件及其方法
公开(公告)号：US20070297120A1
公开(公告)日：2007-12-27
申请号：US11760775
申请日：2007-06-10
申请人： Xiaowei Ren , Daniel J. Lamey
发明人： Xiaowei Ren , Daniel J. Lamey
IPC分类号： H01G4/228
CPC分类号： H01L27/0629 , H01L23/5225 , H01L23/642 , H01L27/0207 , H01L28/40 , H01L28/60 , H01L29/41758 , H01L29/94 , H01L2223/6644 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated shunt capacitor comprises a bottom plate (62), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (64) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate; and a metallization feature (70) disposed about and isolated from at least two sides of the top plate, the metallization feature for coupling the bottom plate to the shield. In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.
摘要翻译：集成分流电容器包括底板（62），覆盖在底板的一部分上的电容器电介质（92），覆盖电容器电介质的顶板（64），覆盖顶板的一部分的屏蔽层（74）以及金属化特征（70），其设置在所述顶板的至少两侧的周围并且与所述顶板的至少两侧隔离，所述金属化特征用于将所述底板耦合到所述屏蔽。在一个实施例中，RF功率晶体管具有包括本文所述的集成分流电容器的阻抗匹配网络。

4. 发明授权

US06222236B1 Protection circuit and method for protecting a semiconductor device 有权
标题翻译：用于保护半导体器件的保护电路和方法
公开(公告)号：US06222236B1
公开(公告)日：2001-04-24
申请号：US09302537
申请日：1999-04-30
申请人： Daniel J. Lamey
发明人： Daniel J. Lamey
IPC分类号： H01L2362
CPC分类号： H01L27/0266 , H01L27/0288 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection circuit (20) includes an active load circuit (22) connected to a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor (21) having a Lightly Doped Drain (LDD). The active load circuit includes a current limiting circuit (26) and a load transistor (27). The ESD protection circuit (20) operates to protect a power transistor (16) from damage due to an electrostatic charge. During an ESD event, the LDMOS transistor (21) enters avalanche breakdown after the voltage of the electrostatic charge exceeds the breakdown voltage of the LDMOS transistor (21). The ESD protection circuit (20) provides a low resistance path during an ESD event to dissipate the electrostatic charge.
摘要翻译：静电放电（ESD）保护电路（20）包括连接到具有轻掺杂漏极（LDD）的侧向扩散金属氧化物半导体（LDMOS）晶体管（21）的有源负载电路（22）。有源负载电路包括限流电路（26）和负载晶体管（27）。 ESD保护电路（20）用于保护功率晶体管（16）免受静电电荷的损害。在ESD事件期间，在静电电荷的电压超过LDMOS晶体管（21）的击穿电压之后，LDMOS晶体管（21）进入雪崩击穿。 ESD保护电路（20）在ESD事件期间提供低电阻路径以耗散静电电荷。

5. 发明授权

US08537512B2 ESD protection using isolated diodes 有权
标题翻译：使用隔离二极管的ESD保护
公开(公告)号：US08537512B2
公开(公告)日：2013-09-17
申请号：US12393166
申请日：2009-02-26
申请人： Daniel J. Lamey , David C. Burdeaux , Olivier Lembeye
发明人： Daniel J. Lamey , David C. Burdeaux , Olivier Lembeye
IPC分类号： H02H9/00
CPC分类号： H01L27/0255 , H01L29/0692 , H01L29/16 , H01L29/861
摘要： An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.
摘要翻译：静电放电（ESD）保护电路（40）耦合在核心电路（22）的输入输出（I / O）焊盘（21）和公共端子（24）之间，以防止ESD事件。电路（40）包括单向ESD钳位（23）和与ESD钳位（23）串联布置成平行相对构造的两个或更多个浮动二极管（42,44），该组合耦合在I / O焊盘 21）和参考端子（24）。在优选的布置中，两串相对的并联耦合二极管（42,44）与每个串中使用不同数量的二极管。这些二极管（42,44）在正向导通（43,45）中工作，因此与反向偏置二极管相比，在ESD事件期间消耗的能量大大降低，并且它们可以具有较小的面积。 I / O焊盘（21）上的信号削波减少，功率消耗减少，芯片面积减少。

6. 发明申请

US20110102077A1 SEMICONDUCTOR DEVICE WITH FEEDBACK CONTROL 有权
标题翻译：具有反馈控制的半导体器件
公开(公告)号：US20110102077A1
公开(公告)日：2011-05-05
申请号：US12609763
申请日：2009-10-30
申请人： Daniel J. Lamey , Michael Guyonnet
发明人： Daniel J. Lamey , Michael Guyonnet
IPC分类号： H03F1/00
CPC分类号： H01L27/0207 , H01L23/4824 , H01L27/0617 , H01L27/0688 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： An electronic element (39′, 39, 40) having feedback control is provided by placing an inductive interposer (42) between the output connection or bus (382) and the input connection or bus (381), wherein the inductive interposer (42) forms part of a closed circuit (47) with the inductive interposer (42) substantially parallel with the output connection or bus (382) and input connection or bus (381) for a distance permitting significant inductive coupling therebetween. In a preferred embodiment, the closed circuit (47) containing the inductive interposer (42) comprises impedance ZT. By including various circuit elements (e.g., resistance, capacitance, and/or inductance) in ZT, the output-to-input feedback can be modified to advantage. This greatly increases the available design freedom, especially for power devices, such as for example, field effect, MOSFET, LDMOS. bipolar and other power devices that use substantially parallel input and output bus structures.
摘要翻译：具有反馈控制的电子元件（39'，39,40）通过将电感式插入器（42）放置在输出连接或总线（382）和输入连接或总线（381）之间来提供，其中感应插入器（42）形成具有与输出连接或总线（382）基本平行的感应插入器（42）和输入连接或总线（381）的一个闭合电路（47）的一部分，距离允许其间的显着的电感耦合。在优选实施例中，包含感应插入器（42）的闭合电路（47）包括阻抗ZT。通过在ZT中包括各种电路元件（例如，电阻，电容和/或电感），输出到输入的反馈可以被有利地修改。这大大增加了可用的设计自由度，特别是对于功率器件，例如场效应，MOSFET，LDMOS。双极和其他功率器件，使用基本上并行的输入和输出总线结构。

7. 发明申请

US20080149981A1 RF POWER TRANSISTOR WITH LARGE PERIPHERY METAL-INSULATOR-SILICON SHUNT CAPACITOR 有权
标题翻译：具有大型外围金属绝缘体 - 硅离子电容器的RF功率晶体管
公开(公告)号：US20080149981A1
公开(公告)日：2008-06-26
申请号：US11961408
申请日：2007-12-20
申请人： Daniel J. Lamey , Xiaowei Ren
发明人： Daniel J. Lamey , Xiaowei Ren
IPC分类号： H01L29/94
CPC分类号： H01L23/66 , H01L23/642 , H01L29/94 , H01L2223/6644 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated MIS capacitor structure comprises a high quality factor shunt capacitor. The integrated MIS capacitor is configured with a large periphery and an external ground via to mitigate resistive losses in the bottom plate of the MIS shunt capacitor.
摘要翻译：集成的MIS电容器结构包括高品质因数并联电容器。集成的MIS电容器配置有大的周边和外部接地通孔，以减轻MIS并联电容器底板中的电阻损耗。

8. 发明授权

US08212321B2 Semiconductor device with feedback control 有权
标题翻译：具有反馈控制的半导体器件
公开(公告)号：US08212321B2
公开(公告)日：2012-07-03
申请号：US12609763
申请日：2009-10-30
申请人： Daniel J. Lamey , Michael Guyonnet
发明人： Daniel J. Lamey , Michael Guyonnet
IPC分类号： H01L27/11
CPC分类号： H01L27/0207 , H01L23/4824 , H01L27/0617 , H01L27/0688 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： An electronic element (39′, 39, 40) having feedback control is provided by placing an inductive interposer (42) between the output connection or bus (382) and the input connection or bus (381), wherein the inductive interposer (42) forms part of a closed circuit (47) with the inductive interposer (42) substantially parallel with the output connection or bus (382) and input connection or bus (381) for a distance permitting significant inductive coupling therebetween. In a preferred embodiment, the closed circuit (47) containing the inductive interposer (42) comprises impedance ZT. By including various circuit elements (e.g., resistance, capacitance, and/or inductance) in ZT, the output-to-input feedback can be modified to advantage. This greatly increases the available design freedom, especially for power devices, such as for example, field effect, MOSFET, LDMOS. bipolar and other power devices that use substantially parallel input and output bus structures.
摘要翻译：具有反馈控制的电子元件（39'，39,40）通过将电感式插入器（42）放置在输出连接或总线（382）和输入连接或总线（381）之间来提供，其中感应插入器（42）形成具有与输出连接或总线（382）基本平行的感应插入器（42）和输入连接或总线（381）的一个闭合电路（47）的一部分，距离允许其间的显着的电感耦合。在优选实施例中，包含感应插入器（42）的闭合电路（47）包括阻抗ZT。通过在ZT中包括各种电路元件（例如，电阻，电容和/或电感），输出到输入的反馈可以被有利地修改。这大大增加了可用的设计自由度，特别是对于功率器件，例如场效应，MOSFET，LDMOS。双极和其他功率器件，使用基本上并行的输入和输出总线结构。

9. 发明授权

US07589370B2 RF power transistor with large periphery metal-insulator-silicon shunt capacitor 有权
标题翻译：具有大外围金属绝缘体 - 硅分流电容器的RF功率晶体管
公开(公告)号：US07589370B2
公开(公告)日：2009-09-15
申请号：US11961408
申请日：2007-12-20
申请人： Daniel J. Lamey , Xiaowei Ren
发明人： Daniel J. Lamey , Xiaowei Ren
IPC分类号： H01L29/94
CPC分类号： H01L23/66 , H01L23/642 , H01L29/94 , H01L2223/6644 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.
摘要翻译：集成的MIS电容器结构具有底部电极，覆盖底部电极的电容器电介质和覆盖电容器电介质的多个电容器顶板。在一种形式中，每个电容器顶板具有主要尺寸和较小的尺寸，其中多个的单个电容器顶板沿着其各自的主要尺寸以阵列的方式彼此靠近并相邻布置。底部电极在多个电容器顶板之间共享。多个导电条中的至少一个沿着相应的电容器顶板的主要尺寸位于每个电容器顶板的相对侧上。该结构还具有接地的顶部金属层和层间电介质。外部接地通孔邻近多个电容器顶板的至少一个侧边缘设置。

10. 发明授权

US06744117B2 High frequency semiconductor device and method of manufacture 有权
标题翻译：高频半导体器件及其制造方法
公开(公告)号：US06744117B2
公开(公告)日：2004-06-01
申请号：US10086061
申请日：2002-02-28
申请人： Christopher P. Dragon , Wayne R. Burger , Daniel J. Lamey
发明人： Christopher P. Dragon , Wayne R. Burger , Daniel J. Lamey
IPC分类号： H01L23552
CPC分类号： H01L29/402 , H01L29/4175 , H01L29/41758 , H01L29/41775 , H01L29/4232 , H01L29/42372 , H01L29/4238 , H01L29/78 , H01L29/7835
摘要： A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.
摘要翻译：一种具有栅极（15），源极（19）和漏极（20）的半导体器件（10），其具有从第一金属层和第二接地屏蔽层图案化的栅极总线（25）和第一接地屏蔽（24）（31）从第二金属层图案化。第一接地屏蔽（24）和第二接地屏蔽（31）降低器件（10）的电容，使其适合于高频应用和塑料封装中的外壳。

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