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1. 发明授权

US5329179A Arrangement for parallel programming of in-system programmable IC logical devices 失效
标题翻译：系统可编程IC逻辑器件的并行编程布置
公开(公告)号：US5329179A
公开(公告)日：1994-07-12
申请号：US957311
申请日：1992-10-05
申请人： Howard Tang , Cyrus Tsui
发明人： Howard Tang , Cyrus Tsui
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054
摘要： A plurality of programmable logic devices are connected in parallel to a programming command generator. A device selector connects individual devices with the programming command generator, thereby permitting the individual devices to be programmed without routing the programming data through other devices. In an alternative embodiment, an identification code is used to place the individual device in a condition to receive programming data. Using the teachings of this invention, programming data may initially be entered into a plurality of devices, and then the data entered in all the devices may be used to program the devices simultaneously. This procedure requires less time than entering data and giving each device the execute command in sequence.
摘要翻译：多个可编程逻辑器件并行连接到编程命令发生器。设备选择器将各个设备与编程命令发生器连接，从而允许编程各个设备，而不通过其他设备路由编程数据。在替代实施例中，使用识别码将单个设备置于接收节目数据的状态。使用本发明的教导，编程数据可以最初被输入到多个设备中，然后可以使用在所有设备中输入的数据来同时对设备进行编程。该过程比输入数据需要更少的时间，并且每个设备按顺序给出执行命令。

2. 发明授权

US06828823B1 Non-volatile and reconfigurable programmable logic devices 有权
标题翻译：非易失性和可重新配置的可编程逻辑器件
公开(公告)号：US06828823B1
公开(公告)日：2004-12-07
申请号：US10439602
申请日：2003-05-16
申请人： Cyrus Tsui , Benny Ma , Om P. Agrawal , Ju Shen , Sam Tsai , Jack Wong , Chan-Chi Jason Cheng
发明人： Cyrus Tsui , Benny Ma , Om P. Agrawal , Ju Shen , Sam Tsai , Jack Wong , Chan-Chi Jason Cheng
IPC分类号： H03K19177
CPC分类号： H03K19/17752 , H03K19/1776 , H03K19/17768
摘要： An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.
摘要翻译：集成电路包括非易失性和易失性存储器，易失性存储器控制集成电路的功能。公开了用于通过一个或多个数据端口对不同类型的存储器进行编程以提供系统内可编程性和动态可重构性的各种技术。如果来自非易失性存储器的数据直接传输到易失性存储器，则不需要外部配置设备。

3. 发明授权

US5130574A Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device 失效
标题翻译：可编程逻辑器件提供产品术语共享和转向可编程逻辑器件的输出
公开(公告)号：US5130574A
公开(公告)日：1992-07-14
申请号：US696461
申请日：1991-05-06
申请人： Ju Shen , Albert L. Chan , Kapil Shankar , Cyrus Tsui
发明人： Ju Shen , Albert L. Chan , Kapil Shankar , Cyrus Tsui
IPC分类号： H03K19/177
CPC分类号： H03K19/17708
摘要： A programmable logic device is disclosed which includes a programmable AND array, a plurality of logic circuits connected to groups of product term outputs from the AND array for performing a logical OR operation of the product term inputs and the programmable logic device includes programmable OR circuitry for selectively connecting one or more of the ORed groups of product terms to one or more outputs of the programmable logic device. The programmable OR circuit permits product term steering and sharing.
摘要翻译：公开了一种可编程逻辑器件，其包括可编程AND阵列，多个逻辑电路连接到来自AND阵列的产品项输出组，用于执行产品项输入的逻辑或运算，并且可编程逻辑器件包括可编程OR电路选择性地将一个或多个OR组的产品术语连接到可编程逻辑器件的一个或多个输出。可编程OR电路允许产品术语转向和共享。

4. 发明授权

US4670708A Short detector for fusible link array using a pair of parallel connected reference fusible links 失效
标题翻译：使用一对并联连接的参考熔断链路的易熔链路阵列的短检测器
公开(公告)号：US4670708A
公开(公告)日：1987-06-02
申请号：US635861
申请日：1984-07-30
申请人： Bob Bosnyak , Albert Chan , Mark Fitzpatrick , Gary Gouldsberry , Cyrus Tsui , Andrew K. Chan
发明人： Bob Bosnyak , Albert Chan , Mark Fitzpatrick , Gary Gouldsberry , Cyrus Tsui , Andrew K. Chan
IPC分类号： G11C29/00 , G01R31/02 , G11C17/00 , G11C29/02 , G11C29/04 , G11C29/50
CPC分类号： G11C29/50008 , G01R31/025 , G11C29/02 , G11C29/50 , G11C17/14
摘要： Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.
摘要翻译：提供电路用于测试易熔链路周围短路的易熔链路阵列。每个链路都是电隔离的，并与一对基准可熔链路进行比较，以检测短路的存在与否。

5. 发明授权

US4634898A TTL buffer circuit incorporating active pull-down transistor 失效
标题翻译：包含有源下拉晶体管的TTL缓冲电路
公开(公告)号：US4634898A
公开(公告)日：1987-01-06
申请号：US554474
申请日：1983-11-22
申请人： Gary Gouldsberry , Albert Chan , Cyrus Tsui , Mark Fitzpatrick
发明人： Gary Gouldsberry , Albert Chan , Cyrus Tsui , Mark Fitzpatrick
IPC分类号： H03K19/013 , H03K19/088 , H03K17/04 , H03K17/60
CPC分类号： H03K19/013 , H03K19/0136 , H03K19/088
摘要： A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.
摘要翻译：独特的双反相缓冲器具有第一装置，用于反转和隔离数字输入信号，第二装置重新转换并进一步隔离输入信号，以及包括输出晶体管94的输出装置。双反相缓冲器配置有主动上拉电阻，输出晶体管92的下降装置。通过双重反转缓冲器的高到低的传播延迟时间和低到高的传播延迟时间通过使用有源下拉装置而减少。输出晶体管的快速关断是通过将晶体管耦合到其基极来实时地将其截止的。在优选实施例中，钳位电路201用于将输出电压保持在最大预定电平，以进一步减少将输出电压降低到逻辑“0”状态所花费的时间。

6. 发明授权

US07038490B1 Delay-matched ASIC conversion of a programmable logic device 有权
标题翻译：可编程逻辑器件的延迟匹配ASIC转换
公开(公告)号：US07038490B1
公开(公告)日：2006-05-02
申请号：US10660814
申请日：2003-09-12
申请人： Satwant Singh , Cyrus Tsui
发明人： Satwant Singh , Cyrus Tsui
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/177 , G06F17/505 , G06F17/5054 , H01L27/118
摘要： An ASIC conversion of a programmable logic device (PLD) is provided. The PLD includes a plurality of logic blocks coupled together by a PLD routing structure. The ASIC includes a plurality of logic blocks corresponding on a one-to-one basis with logic blocks in the PLD and a routing structure corresponding to the programmable routing structure of the PLD. Vias or traces are selectively placed in the ASIC so that logical behavior of its logic blocks matches that implemented in the PLD and the signal propagation delay through the ASIC matches the delay through the PLD.
摘要翻译：提供了可编程逻辑器件（PLD）的ASIC转换。 PLD包括通过PLD路由结构耦合在一起的多个逻辑块。 ASIC包括与PLD中的逻辑块一一对应的多个逻辑块，以及对应于PLD的可编程路由结构的路由结构。通常选择性地将放置在ASIC中的逻辑块的逻辑行为与PLD中实现的逻辑块匹配，并且通过ASIC的信号传播延迟与通过PLD的延迟匹配。

7. 发明授权

US06903573B1 Programmable logic device with enhanced wide input product term cascading 有权
标题翻译：可编程逻辑器件，具有增强的宽输入产品级联级
公开(公告)号：US06903573B1
公开(公告)日：2005-06-07
申请号：US10619711
申请日：2003-07-14
申请人： Jason Cheng , Cyrus Tsui , Satwant Singh , Albert Chan , Ju Shen , Clement Lee
发明人： Jason Cheng , Cyrus Tsui , Satwant Singh , Albert Chan , Ju Shen , Clement Lee
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728
摘要： A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.
摘要翻译：具有逻辑块的可编程设备被配置为将产品项从一个逻辑块级联到另一个逻辑块以增加产品项的逻辑输入宽度。每个逻辑块可以基于从路由结构的输入的选择产生多个乘积项。被配置为接收级联产品项的逻辑块包括与多个产品项对应的多个与门。

8. 发明授权

US06765408B2 Device and method with generic logic blocks 有权
标题翻译：具有通用逻辑块的设备和方法
公开(公告)号：US06765408B2
公开(公告)日：2004-07-20
申请号：US10133106
申请日：2002-04-26
申请人： Jason Cheng , Cyrus Tsui , Satwant Singh , Albert Chen , Ju Shen , Clement Lee
发明人： Jason Cheng , Cyrus Tsui , Satwant Singh , Albert Chen , Ju Shen , Clement Lee
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728
摘要： A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.
摘要翻译：具有通用逻辑块的可编程器件和方法。每个通用逻辑块可配置为执行产品术语逻辑功能和存储器功能，例如RAM，双端口RAM，ROM，CAM，FIFO和开关。

9. 发明授权

US4701695A Short detector for PROMS 失效
标题翻译： PROMS的短检测器
公开(公告)号：US4701695A
公开(公告)日：1987-10-20
申请号：US829260
申请日：1986-02-14
申请人： Albert Chan , Mark Fitzpatrick , Don Goddard , Robert J. Bosnyak , Cyrus Tsui
发明人： Albert Chan , Mark Fitzpatrick , Don Goddard , Robert J. Bosnyak , Cyrus Tsui
IPC分类号： G11C29/02 , G11C29/50 , G01R31/02 , G06F11/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C17/14 , G11C2029/5006
摘要： Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.
摘要翻译：测试电路包括在PROM存储器中，用于检测位线和字线之间的短路以及存储器单元中的短路或泄漏。该电路使所选择的正电压施加在存储器中的所有存储单元上，使得在测试期间可以检测到存储器中的泄漏存储器单元或短路的存在。测试电路在存储器的正常操作期间对存储器没有明显的影响。

10. 发明授权

US4595875A Short detector for PROMS 失效
标题翻译： PROMS的短检测器
公开(公告)号：US4595875A
公开(公告)日：1986-06-17
申请号：US564642
申请日：1983-12-22
申请人： Albert Chan , Mark Fitzpatrick , Don Goddard , Robert J. Bosnyak , Cyrus Tsui
发明人： Albert Chan , Mark Fitzpatrick , Don Goddard , Robert J. Bosnyak , Cyrus Tsui
IPC分类号： G11C17/08 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/50 , G01R15/12
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C17/14 , G11C2029/5006
摘要： Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existance of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.
摘要翻译：测试电路包括在PROM存储器中，用于检测位线和字线之间的短路以及存储器单元中的短路或泄漏。该电路使得所选的正电压可以施加在存储器中的所有存储单元上，使得在测试期间可以检测到存储器中的存储器中存在泄漏的存储器单元或短路。测试电路在存储器的正常操作期间对存储器没有明显的影响。

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