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1. 发明授权

US06628290B1 Graphics pipeline selectively providing multiple pixels or multiple textures 有权
标题翻译：图形管道选择性地提供多个像素或多个纹理
公开(公告)号：US06628290B1
公开(公告)日：2003-09-30
申请号：US09677941
申请日：2000-10-02
申请人： David B. Kirk , Gopal Solanki , Curtis Priem , Walter Donovan , Joe L. Yeun
发明人： David B. Kirk , Gopal Solanki , Curtis Priem , Walter Donovan , Joe L. Yeun
IPC分类号： G06T120
CPC分类号： G06T15/005
摘要： A method and graphics accelerator apparatus for pipelined generation of output values for a sequence of pixels, with generation of output values for each of at least two textured pixels during each pipeline clock interval. The apparatus includes a combiner stage capable of producing output values during each clock interval of the pipeline, wherein the output values are indicative of a blend of a plurality of textures with a single pixel when the combiner stage operates in a first mode, and the output values are indicative of a blend of an individual texture with two pixels when the combiner stage operates in a second mode.
摘要翻译：一种用于流水线生成像素序列的输出值的方法和图形加速器装置，在每个流水线时钟间隔期间产生至少两个纹理像素中的每一个的输出值。该装置包括能够在流水线的每个时钟间隔期间产生输出值的组合器级，其中当组合器级在第一模式下操作时，输出值指示多个纹理与单个像素的混合，并且输出当组合器级在第二模式下操作时，值表示具有两个像素的个体纹理的混合。

2. 发明授权

US6092124A Method and apparatus for accelerating the rendering of images 失效
标题翻译：用于加速图像渲染的方法和装置
公开(公告)号：US6092124A
公开(公告)日：2000-07-18
申请号：US61719
申请日：1998-04-17
申请人： Curtis Priem , Rick Iwamoto , Stephen Johnson
发明人： Curtis Priem , Rick Iwamoto , Stephen Johnson
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.
摘要翻译：一种直接存储器访问（DMA）电路，其与输入/输出设备物理定位，DMA电路存储指向数据结构的第一参考值，该数据结构描述系统存储器的缓冲部分，其中存储数据以传送到I 确定下一个数据序列开始的系统存储器的缓冲部分内的位置的值，以及确定下一个数据序列的系统存储器的缓冲部分内的位置的值要复制到I / O设备，DMA电路包括用于从系统存储器的缓冲器部分读取数据的电路，该数据从下一个数据序列将被复制的位置开始，并将读出的数据写入I / O设备。

3. 发明授权

US6023738A Method and apparatus for accelerating the transfer of graphical images 失效
标题翻译：用于加速图形图像传送的方法和装置
公开(公告)号：US6023738A
公开(公告)日：2000-02-08
申请号：US50852
申请日：1998-03-30
申请人： Curtis Priem , David S. H. Rosenthal , Rick Iwamoto
发明人： Curtis Priem , David S. H. Rosenthal , Rick Iwamoto
IPC分类号： G06F3/14 , G06F13/28 , G09G5/00 , G09G5/36 , G06F13/00
CPC分类号： G09G5/363 , G06F13/28 , G06F3/14
摘要： A direct memory access (DMA) arrangement having a DMA circuit which is positioned with an input/output device, the DMA circuit including a first register for storing a reference value pointing to a first data structure established by an application program which includes details of a transfer buffer in memory in which data is stored for transfer to the I/O device, two additional registers for storing an address and a range at which the data is stored within the transfer buffer in memory, and a fourth register for storing a reference value pointing to a second data structure which includes details describing a notification area of memory at which a notification from the DMA circuit that a transfer of data has been completed may be stored.
摘要翻译：一种直接存储器访问（DMA）装置，其具有与输入/输出装置一起定位的DMA电路，所述DMA电路包括用于存储指向由应用程序建立的第一数据结构的参考值的第一寄存器，该参考值包括：存储器中的数据传输缓冲器，其中存储数据以传送到I / O设备，两个用于存储地址的附加寄存器和数据存储在存储器中的传送缓冲器内的范围;以及第四寄存器，用于存储参考值指向第二数据结构，其包括描述存储器的通知区域的细节，在该通知区域可以存储来自DMA电路的通知已经完成数据传送的通知。

4. 发明授权

US5721947A Apparatus adapted to be joined between the system I/O bus and I/O devices which translates addresses furnished directly by an application program 失效
标题翻译：适于连接在系统I / O总线和I / O设备之间的设备，其转换由应用程序直接提供的地址
公开(公告)号：US5721947A
公开(公告)日：1998-02-24
申请号：US441043
申请日：1995-05-15
申请人： Curtis Priem , David S. H. Rosenthal
发明人： Curtis Priem , David S. H. Rosenthal
IPC分类号： G06F12/02 , G06F13/00
CPC分类号： G06F12/0292 , G06F2212/206
摘要： A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit joined to the system input/output bus for translating addresses on the system input/output bus to physical input/output device addresses.
摘要翻译：一种包括中央处理单元，系统输入/输出总线，输入/输出设备和连接到系统输入/输出总线的输入/输出控制单元的计算机系统，用于将系统输入/输出总线上的地址转换为物理输入 /输出设备地址。

5. 发明授权

US5696990A Method and apparatus for providing improved flow control for input/output operations in a computer system having a FIFO circuit and an overflow storage area 失效
标题翻译：一种用于在具有FIFO电路和溢出存储区域的计算机系统中为输入/输出操作提供改进的流量控制的方法和装置
公开(公告)号：US5696990A
公开(公告)日：1997-12-09
申请号：US441554
申请日：1995-05-15
申请人： David S. H. Rosenthal , Curtis Priem
发明人： David S. H. Rosenthal , Curtis Priem
IPC分类号： G06F5/06 , G06F13/00
CPC分类号： G06F5/06
摘要： A system which uses an arrangement of FIFO buffers which include circuitry to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer. Each FIFO buffer includes a flow control register which stores a value which indicates the amount of space available in the FIFO to which data may be written. In order to allow for situations in which data is available at a FIFO buffer which cannot be immediately utilized for some reason, an overflow storage area is provided for storing data transferred to the FIFO buffer in excess of the number of stages of the FIFO circuit which are available to store data. The flow control circuitry also includes circuitry for assuring that data which is placed in the overflow storage area is handled in the appropriate sequence.
摘要翻译：使用FIFO缓冲器的布置的系统，其包括用于确保由应用程序写入FIFO缓冲器的数据不会溢出FIFO缓冲器的电路。每个FIFO缓冲器包括流控制寄存器，其存储指示可写入数据的FIFO中可用的空间量的值。为了允许由于某种原因而不能立即使用的FIFO缓冲器中的数据可用的情况，提供溢出存储区域用于存储传输到FIFO缓冲器的数据超过FIFO电路的级数，可用于存储数据。流量控制电路还包括用于确保以适当顺序处理放置在溢出存储区域中的数据的电路。

6. 发明授权

US5654742A Method and apparatus for providing operations affecting a frame buffer without a row address strobe cycle 失效
标题翻译：用于提供影响帧缓冲器而不具有行地址选通周期的操作的方法和装置
公开(公告)号：US5654742A
公开(公告)日：1997-08-05
申请号：US451476
申请日：1995-05-26
申请人： Curtis Priem , Chris Malachowsky , Shuen Chin Chang , Hai Duy Ho
发明人： Curtis Priem , Chris Malachowsky , Shuen Chin Chang , Hai Duy Ho
IPC分类号： G06F12/02 , G06F12/00 , G09G5/00 , G09G5/39 , G11C7/10
CPC分类号： G11C7/1087 , G09G5/39 , G11C7/103 , G11C7/1033 , G11C7/1051 , G11C7/1078
摘要： A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.
摘要翻译：设计用于允许不需要RAS周期来实现不涉及新行地址的帧缓冲操作的帧缓冲器。消除用于地址加载和类似功能的RAS周期大大加速了帧缓冲器的操作，这两个功能不涉及存储器阵列地址和那些涉及存储器阵列地址的功能。

7. 发明授权

US5638535A Method and apparatus for providing flow control with lying for input/output operations in a computer system 失效
标题翻译：用于在计算机系统中提供用于输入/输出操作的流量控制的方法和装置
公开(公告)号：US5638535A
公开(公告)日：1997-06-10
申请号：US441405
申请日：1995-05-15
申请人： David S. H. Rosenthal , Curtis Priem , Chris A. Malachowsky
发明人： David S. H. Rosenthal , Curtis Priem , Chris A. Malachowsky
IPC分类号： G06F5/06 , G06F12/00
CPC分类号： G06F5/06
摘要： A flow control circuit for a computer system including a first-in first-out buffer including a register for storing a value indicating the number of stages of the FIFO which are available to store data, circuitry for detecting whether an input/output device is able to process data more rapidly than the FIFO is emptied, and circuitry for providing an value greater than the number of stages actually available for storage in the FIFO if the input/output device is able to process data more rapidly than the FIFO is emptied.
摘要翻译：一种用于计算机系统的流量控制电路，包括先入先出缓冲器，其包括用于存储指示可用于存储数据的FIFO的级数的值的寄存器，用于检测输入/输出设备是否能够比FIFO清空更快速地处理数据，以及如果输入/输出设备能够比FIFO清空更快的处理数据，则提供大于实际可用于存储在FIFO中的级数的值的电路。

8. 发明授权

US5539430A Pipelined read write operations in a high speed frame buffer system 失效
标题翻译：在高速帧缓冲系统中进行流水线读写操作
公开(公告)号：US5539430A
公开(公告)日：1996-07-23
申请号：US145483
申请日：1993-10-29
申请人： Curtis Priem , Shuen C. Chang , Hai D. Ho
发明人： Curtis Priem , Shuen C. Chang , Hai D. Ho
IPC分类号： G06F12/00 , G06F3/147 , G09G5/00 , G09G5/02 , G09G5/39 , G09G5/395 , G11C7/10 , G09G1/02
CPC分类号： G11C7/1039 , G09G5/024 , G09G5/395 , G09G2310/04 , G09G2360/126
摘要： A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.
摘要翻译：一种帧缓冲器，包括用于存储指示要显示在输出显示器上的像素的数据的存储单元阵列，用于选择位于阵列中的存储单元的行寻址解码装置和列地址解码装置，用于将行地址传送到行寻址解码装置，在断言行地址选通信号时，用于将列地址传送到列地址解码装置，用于在断言第一列地址选通信号时进行解码的装置，用于锁存列地址的装置和完成所述列地址选通信号所需的任何数据在第一列地址选通信号期间的访问，用于访问特定列的装置，其特征列的地址已经在锁存待访问的列的下一个后续地址以及在下一次后续期间完成下一次访问所需的任何数据时被锁存列地址选通信号跟随第一列地址选通信号。

9. 发明授权

US5504855A Method and apparatus for providing fast multi-color storage in a frame buffer 失效
标题翻译：用于在帧缓冲器中提供快速多色存储的方法和装置
公开(公告)号：US5504855A
公开(公告)日：1996-04-02
申请号：US145756
申请日：1993-10-29
申请人： Curtis Priem , Chris Malachowsky , Rick Silverman , Shuen C. Chang
发明人： Curtis Priem , Chris Malachowsky , Rick Silverman , Shuen C. Chang
IPC分类号： G09G5/00 , G09G5/02 , G09G5/04 , G09G5/393 , G11C7/10 , G06F15/00
CPC分类号： G09G5/022 , G09G5/393 , G11C7/1078
摘要： A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of which may be loaded with color values prior to writing to the frame buffer. Selection means are provided for selecting pixel data from the bus, from a first of the color value registers, from the second of the color value registers, or from both color value registers simultaneously. When data is written to the frame buffer from color value registers it may be written to a number of pixel positions simultaneously.
摘要翻译：一种用于加速在输出显示装置上显示图形数据的帧缓冲器，该帧缓冲器包括一对颜色值寄存器，每个颜色值寄存器可以在写入帧缓冲器之前加载颜色值。选择装置用于从总线，颜色值寄存器中的第一个，颜色值寄存器中的第二个或两个色值寄存器同时选择像素数据。当数据从彩色值寄存器写入帧缓冲器时，它可以同时写入多个像素位置。

10. 发明授权

US5287487A Predictive caching method and apparatus for generating a predicted address for a frame buffer 失效
标题翻译：用于生成帧缓冲器的预测地址的预测缓存方法和装置
公开(公告)号：US5287487A
公开(公告)日：1994-02-15
申请号：US74703
申请日：1993-06-09
申请人： Curtis Priem , Chris Malachowsky , Robert Rocchetti , David Rosenthal
发明人： Curtis Priem , Chris Malachowsky , Robert Rocchetti , David Rosenthal
IPC分类号： G06F12/08 , G06F12/02 , G06F13/00
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6026
摘要： A predictive caching system for use in computer system having at least one portion of memory in which information is stored for retrieval, a general cache used to speed the operation of accessing such memory, and a processor for controlling the access of the memory comprising apparatus for discerning a pattern of access of the memory, apparatus operating in response to the pattern determined by the apparatus for discerning a pattern of access of the memory for determining a next address which will probably accessed in such memory if the pattern discerned continues, and apparatus for storing the information at the next address determined prior to the next access of the memory whereby the information at the next address is available without the need to access the memory.
摘要翻译：一种用于计算机系统的预测性高速缓存系统，具有至少一部分存储器，其中存储有用于检索的信息，用于加速访问这种存储器的操作的通用缓存器，以及用于控制存储器的访问的处理器，识别所述存储器的访问模式，所述设备响应于由所述设备确定的模式而工作，所述模式用于识别所述存储器的访问模式，用于确定如果所识别的所述模式继续则在所述存储器中可能访问的下一个地址，以及用于将信息存储在下一次访问存储器之前确定的下一个地址处，由此下一个地址处的信息可用，而不需要访问存储器。

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