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1. 发明授权

US07704746B1 Method of detecting leakage from geologic formations used to sequester CO2 有权
标题翻译：检测用于隔离二氧化碳的地质地层泄漏的方法
公开(公告)号：US07704746B1
公开(公告)日：2010-04-27
申请号：US12351348
申请日：2009-01-09
申请人： Curt White , Arthur Wells , J. Rodney Diehl , Brian Strazisar
发明人： Curt White , Arthur Wells , J. Rodney Diehl , Brian Strazisar
IPC分类号： G01N37/00
CPC分类号： G01M3/20 , C09K8/035 , E21B41/0064 , E21B47/1015 , G01N30/7206 , Y02C10/14 , Y10T436/13
摘要： The invention provides methods for the measurement of carbon dioxide leakage from sequestration reservoirs. Tracer moieties are injected along with carbon dioxide into geological formations. Leakage is monitored by gas chromatographic analyses of absorbents. The invention also provides a process for the early leak detection of possible carbon dioxide leakage from sequestration reservoirs by measuring methane (CH4), ethane (C2H6), propane (C3H8), and/or radon (Rn) leakage rates from the reservoirs. The invention further provides a method for branding sequestered carbon dioxide using perfluorcarbon tracers (PFTs) to show ownership.
摘要翻译：本发明提供了用于测量隔离储存器中二氧化碳泄漏的方法。示踪剂部分与二氧化碳一起注入地质构造。通过吸附剂的气相色谱分析来监测泄漏。本发明还提供了一种用于通过从储层测量甲烷（CH 4），乙烷（C 2 H 6），丙烷（C 3 H 8）和/或氡（R n）泄漏速率来早期泄漏检测来自封存储存器的二氧化碳泄漏的方法。本发明还提供了使用全氟化碳示踪剂（PFT）来标记隔离二氧化碳以显示所有权的方法。

2. 发明授权

US06961877B2 System and method for in-line error correction for storage systems 有权
标题翻译：存储系统的在线纠错系统和方法
公开(公告)号：US06961877B2
公开(公告)日：2005-11-01
申请号：US10199911
申请日：2002-07-19
申请人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
发明人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
IPC分类号： G11B20/18 , G06F11/00
CPC分类号： G06F11/1064 , G11B20/18 , H03M13/05
摘要： The present invention provides a method and system for performing in-line error correction in a disk storage system. The system includes an error correction (ECC) module; and a first memory storage device, wherein the first memory storage device and the error correction module simultaneously receive data from a storage disk before being buffered for transfer to a host system. The ECC module provides error correction mask before any data is transferred from the first memory storage device to a second memory buffer.
摘要翻译：本发明提供一种用于在盘存储系统中进行在线纠错的方法和系统。该系统包括纠错（ECC）模块; 以及第一存储器存储设备，其中所述第一存储器存储设备和所述纠错模块在被缓存以在传送到主机系统之前同时从存储盘接收数据。 ECC模块在将任何数据从第一存储器存储设备传送到第二存储器缓冲器之前提供纠错掩码。

3. 发明授权

US5666515A Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address 失效
标题翻译：具有多个模块和总线上的存储器的信息处理系统，其中任何模块可以通过向尝试在锁定地址读取的其他模块发送重试信号来锁定存储器的可寻址部分
公开(公告)号：US5666515A
公开(公告)日：1997-09-09
申请号：US759996
申请日：1996-12-04
申请人： Theodore Curt White , Jayesh Vrajlal Sheth , Kha Nguyen , Dan Trong Tran
发明人： Theodore Curt White , Jayesh Vrajlal Sheth , Kha Nguyen , Dan Trong Tran
IPC分类号： G06F12/14 , G06F13/18
CPC分类号： G06F12/1425
摘要： Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location. During this Read-Modify-Write operation, the input/output unit also monitors the system bus for any attempts or requests to read data from, or write data to, the memory address for which the Read-Modify-Write operation is being performed. In such event, a signal is sent to the module making such attempt or request, asking or telling that module to wait. That signal is removed when that Read-Modify-Write operation is completed.
摘要翻译：提供了装置和方法，用于防止在存储器位置被修改，更新等时访问存储器位置。当外围设备希望在存储器位置处完成这种改变时，它将改变的数据及其预期的存储器地址提供给输入/输出单元。输入/输出单元包括多个单独控制的多路复用器，多路复用器的数量优选地被选择为对应于存储器数据字或分组除以外围数据字的大小（以比特为单位）的大小（以比特为单位）。输入/输出单元将所请求的存储器位置的数据读入输入缓冲器，将不被修改的数据部分与由外设提供的数据进行组合，并将结果发回相同的存储位置。在该读 - 修改 - 写操作期间，输入/输出单元还监视系统总线，用于从执行读 - 修改 - 写操作的存储器地址的任何尝试或请求读取数据或将数据写入数据。在这种情况下，信号被发送到模块进行这样的尝试或请求，询问或告诉该模块等待。当该读 - 修改 - 写操作完成时，该信号被去除。

4. 发明授权

US5809533A Dual bus system with multiple processors having data coherency maintenance 失效
标题翻译：具有多个处理器的双总线系统具有数据一致性维护
公开(公告)号：US5809533A
公开(公告)日：1998-09-15
申请号：US797216
申请日：1997-02-11
申请人： Dan Trong Tran , Paul Bernard Ricci , Jayesh Vrajlal Sheth , Theodore Curt White , Richard Allen Cowgill
发明人： Dan Trong Tran , Paul Bernard Ricci , Jayesh Vrajlal Sheth , Theodore Curt White , Richard Allen Cowgill
IPC分类号： G06F13/42 , G06F13/16
CPC分类号： G06F13/4217
摘要： A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.
摘要翻译：一种多模块网络，具有使用公共总线协议的双系统总线，该公共总线协议使用存储通过高速缓冲存储器支持处理器模块，并且使用包括用于维持高速缓存一致性的间谍单元的接口模块的非存储高速缓存存储器的处理器模块，仲裁器模块，使任何特定的模块不会被饿死。维护处理器将网络组织为联合系统，其中通过处理器单元的存储和非存储都可以利用双系统总线中的一个或分配系统，其中一个总线专用于存储处理器单元和一个总线总线专用于通过处理器单元的非存储。

5. 发明授权

US5737756A Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue 失效
标题翻译：双总线计算机网络使用具有双间谍模块的双总线，能够通过缓存清除处理器的无效队列，同时提供对无效队列的不完全访问的重试周期
公开(公告)号：US5737756A
公开(公告)日：1998-04-07
申请号：US701039
申请日：1996-08-21
申请人： Theodore Curt White , Jayesh Vrajlal Sheth
发明人： Theodore Curt White , Jayesh Vrajlal Sheth
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by a system bus spy module which monitors the addresses of new data words selected for a write operation.
摘要翻译：一种用于增强无存储周期快速的系统和方法，所述处理器具有保存4字数据分组的存储直接高速缓存，由此无效队列保存在高速缓存中无效的数据的地址，并且所述地址由系统总线间谍模块提供，所述系统总线间谍模块监视为写入操作选择的新数据字的地址。

6. 发明授权

US5696937A Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses 失效
标题翻译：缓存控制器利用状态机来控制具有双系统总线的网络中的无效
公开(公告)号：US5696937A
公开(公告)日：1997-12-09
申请号：US431366
申请日：1995-04-28
申请人： Theodore Curt White , Jayesh Vrajlal Sheth
发明人： Theodore Curt White , Jayesh Vrajlal Sheth
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0831
摘要： A state machine system is used to control a cache controller in a network involving the operations of a processor having a store-through cache and operations involving an invalidation queue which is filled by a spy module which monitors dual system busses to select addresses of words which appear for write operations.
摘要翻译：状态机系统用于控制网络中的高速缓存控制器，其涉及具有存储直通缓存的处理器的操作，以及涉及无效队列的操作，所述无效队列由监视双系统总线的间谍模块填充以选择字的地址出现写入操作。

7. 发明申请

US20120192036A1 SYSTEM AND METHOD FOR IN-LINE ERROR CORRECTION FOR STORAGE SYSTEMS 有权
标题翻译：用于存储系统的在线错误校正的系统和方法
公开(公告)号：US20120192036A1
公开(公告)日：2012-07-26
申请号：US13400321
申请日：2012-02-20
申请人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
发明人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1064 , G11B20/18 , H03M13/05
摘要： A disk controller comprising a disk formatter configured to receive data being transferred between a disk and a host. A buffer controller is in communication with the disk formatter, a buffer configured to store the data being transferred between the disk and the host, and the host. The buffer is external to each of the disk controller and the host. The buffer controller is configured to regulate transfer of the data between the buffer and the disk formatter. An error correction module is in communication with the disk formatter and the buffer controller. The error correction module is configured to generate an error correction mask to correct errors in the data. The error correction mask is applied to the data prior to the buffer controller transferring the data to the buffer.
摘要翻译：一种磁盘控制器，包括被配置为接收在磁盘和主机之间传送的数据的磁盘格式器。缓冲器控制器与磁盘格式器通信，缓冲器被配置为存储在盘和主机之间传送的数据以及主机。缓冲区位于每个磁盘控制器和主机的外部。缓冲器控制器被配置为调节缓冲器和盘格式器之间的数据传送。纠错模块与磁盘格式器和缓冲器控制器通信。误差校正模块被配置为产生纠错掩模以校正数据中的错误。在缓冲器控制器将数据传送到缓冲器之前，将错误校正掩码应用于数据。

8. 发明授权

US5673415A High speed two-port interface unit where read commands suspend partially executed write commands 失效
标题翻译：高速双端口接口单元，其中读命令暂停部分执行写命令
公开(公告)号：US5673415A
公开(公告)日：1997-09-30
申请号：US698212
申请日：1996-08-14
申请人： Kha Nguyen , Theodore Curt White , Bruce Edward Moolenaar
发明人： Kha Nguyen , Theodore Curt White , Bruce Edward Moolenaar
IPC分类号： G06F3/06 , G06F12/00 , G06F13/00
CPC分类号： G06F3/0601 , G06F2003/0692
摘要： In accordance with the present invention, a high speed two-part storage interface unit includes--1) a primary I/O port (input/output port) that couples to a plurality of data processing modules; 2) a secondary I/O port that couples to a main memory module, 3) input circuits for receiving three types of write commands and one type of read command from the data processing modules, 4) several write execution modules which are serially-coupled to a time-shared memory, and 5) a control circuit by which the write commands and read commands are performed. In one preferred embodiment, write commands are executed over several clock cycles by passing each such command with its write data word through the write execution modules in a pipelined fashion; read commands are executed at a rate of one command per clock cycle; a read command temporarily preempts the execution of any write command; an interrupt signal on the secondary I/O port stops the execution of read commands and write commands from the primary I/O port and enables data words to be transferred on the secondary I/O port; and write commands can be received on the primary I/O port while data is being transferred on the secondary I/O port.
摘要翻译：根据本发明，高速两部分存储接口单元包括：1）耦合到多个数据处理模块的主I / O端口（输入/输出端口）; 2）耦合到主存储器模块的辅助I / O端口，3）用于从数据处理模块接收三种写入命令和一种类型的读取命令的输入电路，4）串行耦合的多个写入执行模块到时间共享存储器，以及5）执行写入命令和读取命令的控制电路。在一个优选实施例中，通过以流水线方式通过写入执行模块传递每个这样的命令与其写入数据字，在几个时钟周期内执行写入命令; 读取命令以每个时钟周期的一个命令的速率执行; 读命令临时抢占执行任何写命令; 辅助I / O端口上的中断信号停止执行读取命令并从主I / O端口写入命令，并使数据字能够在辅助I / O端口上传输; 并且在辅助I / O端口上传输数据时，可以在主I / O端口上接收写入命令。

9. 发明授权

US08402323B2 System and method for in-line error correction for storage systems 有权
标题翻译：存储系统的在线纠错系统和方法
公开(公告)号：US08402323B2
公开(公告)日：2013-03-19
申请号：US13400321
申请日：2012-02-20
申请人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
发明人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G11B20/18 , H03M13/05
摘要： A disk controller comprising a disk formatter configured to receive data being transferred between a disk and a host. A buffer controller is in communication with the disk formatter, a buffer configured to store the data being transferred between the disk and the host, and the host. The buffer is external to each of the disk controller and the host. The buffer controller is configured to regulate transfer of the data between the buffer and the disk formatter. An error correction module is in communication with the disk formatter and the buffer controller. The error correction module is configured to generate an error correction mask to correct errors in the data. The error correction mask is applied to the data prior to the buffer controller transferring the data to the buffer.
摘要翻译：一种磁盘控制器，包括被配置为接收在磁盘和主机之间传送的数据的磁盘格式器。缓冲器控制器与磁盘格式化器通信，缓冲器被配置为存储在盘和主机之间传送的数据以及主机。缓冲区位于每个磁盘控制器和主机的外部。缓冲器控制器被配置为调节缓冲器和盘格式器之间的数据传送。纠错模块与磁盘格式器和缓冲器控制器通信。误差校正模块被配置为产生纠错掩模以校正数据中的错误。在缓冲器控制器将数据传送到缓冲器之前，将错误校正掩码应用于数据。

10. 发明授权

US08122299B2 System and method for in-line error correction for storage systems 有权
标题翻译：存储系统的在线纠错系统和方法
公开(公告)号：US08122299B2
公开(公告)日：2012-02-21
申请号：US11231312
申请日：2005-09-20
申请人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
发明人： Yujun Si , Theodore Curt White , Stanley Ka Fai Cheong
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G11B20/18 , H03M13/05
摘要： The present invention provides a method and system for performing in-line error correction in a disk storage system. The system includes an error correction (ECC) module; and a first memory storage device, wherein the first memory storage device and the error correction module simultaneously receive data from a storage disk before being buffered for transfer to a host system. The ECC module provides error correction mask before any data is transferred from the first memory storage device to a second memory buffer.
摘要翻译：本发明提供一种用于在盘存储系统中进行在线纠错的方法和系统。该系统包括纠错（ECC）模块; 以及第一存储器存储设备，其中所述第一存储器存储设备和所述纠错模块在被缓存以在传送到主机系统之前同时从存储盘接收数据。 ECC模块在将任何数据从第一存储器存储设备传送到第二存储器缓冲器之前提供纠错掩码。

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