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1. 发明申请

US20070187468A1 Low inductance via arrangement for multilayer ceramic substrates 失效
标题翻译：用于多层陶瓷衬底的低电感通孔布置
公开(公告)号：US20070187468A1
公开(公告)日：2007-08-16
申请号：US11355713
申请日：2006-02-16
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Roger Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Roger Weekly
IPC分类号： B23K5/20 , B23K20/10 , B23K1/06
CPC分类号： H05K1/162 , H01L23/49827 , H01L23/50 , H01L23/642 , H01L2924/0002 , H05K1/0306 , H05K3/4611 , H05K3/4629 , H05K2201/09609 , H05K2201/09627 , Y10T29/49117 , Y10T29/49155 , H01L2924/00
摘要： A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.
摘要翻译：提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。这种减少是通过引入T-jogs和附加通孔来实现的。这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

2. 发明申请

US20070260444A1 System DC Analysis Methodology 有权
标题翻译：系统直流分析方法
公开(公告)号：US20070260444A1
公开(公告)日：2007-11-08
申请号：US11380058
申请日：2006-04-25
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Gia-Harvey Truong , Roger Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Gia-Harvey Truong , Roger Weekly
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of power delivery analysis and design for a hierarchical system including building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, assembling a system model from the models contained in the repository, flattening the system model, and running a simulation on the flattened system model.
摘要翻译：一种用于分层系统的功率传递分析和设计的方法，包括构建与分层系统的每个元件相对应的模型，编译包含与分层系统的每个元件相对应的模型的存储库，从包含的模型组装系统模型存储库，平整系统模型，并在平面化系统模型上运行仿真。

3. 发明申请

US20070239387A1 Apparatus and Method for Selectively Monitoring Multiple Voltages in an IC or other Electronic Chip 失效
标题翻译：用于选择性监测IC或其他电子芯片中的多个电压的装置和方法
公开(公告)号：US20070239387A1
公开(公告)日：2007-10-11
申请号：US11278848
申请日：2006-04-06
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Truong , Roger Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm O'Reilly , Bao Truong , Roger Weekly
IPC分类号： G06F19/00
CPC分类号： G01R19/16552
摘要： An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. In embodiments of the invention, only a single pair of C4 pins is required for all voltage monitoring activity. One useful embodiment is directed to apparatus for monitoring the level of voltage associated with each domain in a partitioned chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.
摘要翻译：提供了一种用于监视分区电子芯片的多个电压域的每个域中可用电压的装置和方法。在本发明的实施例中，对于所有电压监视活动，仅需要一对C4引脚。一个有用的实施例涉及用于监视与分区芯片中的每个域相关联的电压电平的装置。该装置包括耦合到芯片的单个导电链路，并且还包括具有单个输出和多个可切换输入的域选择网络，该输出连接到单个导电链路，并且两个输入端被连接以监视相应的电压电平的多个电压域中的两个。设置控制机构以操作选择网络，以便选择性地将输入中的一个连接到单个导电链路，并且电子芯片外部的传感器装置被连接以测量所监视的相应的多个电压域使用单个导电链路。

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