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    • 4. 发明申请
    • BURNER INSTALLATION
    • 燃烧器安装
    • US20100159407A1
    • 2010-06-24
    • US12641693
    • 2009-12-18
    • Colin Harris
    • Colin Harris
    • F23D14/46
    • F23D14/72F23D2208/10F23N5/245F23N2029/20F23N2900/05005
    • A burner installation includes a burner housing (1), a burner mounted in the burner housing, and a burner flame monitoring device (14) for detecting the presence of a flame in the burner. The monitoring device (14) is able to provide a signal indicating the presence of the flame in the burner, the monitoring device being detachably mounted on the burner housing (1). A magnet (22) and sensor (17) for detecting the proximity of the magnet are provided. One of the magnet (22) and sensor (17) is secured in fixed relationship to the monitoring device (14) and the other of the magnet and sensor is secured in fixed relationship to the burner housing (1), whereby the sensor (17) is able to detect if the monitoring device (14) is detached from the burner housing.
    • 燃烧器设备包括燃烧器壳体(1),安装在燃烧器壳体中的燃烧器和用于检测燃烧器中存在火焰的燃烧器火焰监测装置(14)。 监视装置(14)能够提供指示燃烧器中存在火焰的信号,该监视装置可拆卸地安装在燃烧器壳体(1)上。 提供了用于检测磁体接近度的磁体(22)和传感器(17)。 磁体(22)和传感器(17)中的一个以固定的关系固定在监视装置(14)上,磁体和传感器中的另一个固定在燃烧器壳体(1)上,由此传感器 )能够检测监测装置(14)是否与燃烧器壳体分离。
    • 5. 发明授权
    • Tristatable output driver for use with 3.3 or 5 volt CMOS logic
    • 可调输出驱动器,用于3.3或5伏CMOS逻辑
    • US5850153A
    • 1998-12-15
    • US861575
    • 1997-05-22
    • Colin HarrisCurtis B. Lapadat
    • Colin HarrisCurtis B. Lapadat
    • H03K19/0175H03K19/003H03K19/094H03K19/00H03K19/0185
    • H03K19/00315H03K19/09429
    • A tri-state output driver comprised of a pair of complementary field effect transistors (CMOS FETs) having sources and drains connected in a series circuit between a voltage rail and ground, apparatus for applying similar logic high and low input signals to respective gates of the FETs whereby an output terminal connected in a circuit between the sources and drains of the FETs is driven toward ground or the voltage rail respectively, or opposite polarity input signals to the gates for causing the FETs to assume a high impedance, and apparatus for maintaining a voltage across the source and drain of the FET which is connected in a circuit between the voltage rail and the output terminal, at less than a lower of an FET threshold of conduction voltage or diode turn-on voltage greater than the voltage of the voltage rail, during the high impedance state, so as to maintain the latter FET in a high impedance state even when a voltage at the output terminal is equal to a voltage which is higher than an FET threshold of conduction or diode turn-on voltage greater than the voltage of the voltage rail.
    • 三态输出驱动器由一对具有连接在电压轨和地之间的串联电路中的源极和漏极的互补场效应晶体管(CMOS FET)组成,用于将类似的逻辑高和低输入信号施加到相应的栅极 FET,其中连接在FET的源极和漏极之间的电路中的输出端子分别被驱动到接地或电压轨,或者相反极性输入到栅极的输入信号,以使FET产生高阻抗;以及用于维持 在电压轨和输出端之间的电路中连接的FET的源极和漏极之间的电压小于导通电压的FET阈值或比电压轨的电压大的二极管导通电压的下限 在高阻抗状态期间,即使当输出端子处的电压等于高电平时,也能将后一个FET保持在高阻抗状态 呃比导通或二极管导通电压的FET阈值大于电压轨的电压。
    • 6. 发明授权
    • Compact CMOS analog crosspoint switch matrix
    • 紧凑型CMOS模拟交叉点开关矩阵
    • US5481125A
    • 1996-01-02
    • US85458
    • 1993-06-29
    • Colin Harris
    • Colin Harris
    • H01L29/78H01L21/8234H01L27/088H01L27/112H01L27/118H03K17/693H01L27/10
    • H01L27/112H01L27/11803
    • An integrated circuit analog crosspoint switch FET array which utlilizes considerably reduced silicon substrate area than previously. In a preferred embodiment, pairs of the separate diffused regions of different FETs which are connected to the same input are common, forming separate single diffused regions. The separate single diffused regions and the central single diffused regions alternate continuously in a row, separated by the channel regions forming the various transistors. The result is a continuous row of transistors having common diffused regions, except for the transistors at the end of the row, which have their outer diffused regions not in common with any other.
    • 一种集成电路模拟交叉点开关FET阵列,其比以前大大减少了硅衬底面积。 在优选实施例中,连接到相同输入的不同FET的单独扩散区域是成对的,形成分开的单个扩散区域。 分离的单个扩散区域和中央单个扩散区域连续地交替排列,由形成各种晶体管的沟道区域分开。 结果是具有共同扩散区域的连续行晶体管,除了在行末端的晶体管,其外部扩散区域与其他扩散区域不共同。