专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08557646B2 Method for fabricating a vertical transistor 有权
标题翻译：垂直晶体管的制造方法
公开(公告)号：US08557646B2
公开(公告)日：2013-10-15
申请号：US13410102
申请日：2012-03-01
申请人： Meng-Hsien Chen , Chung-Yung Ai , Chih-Wei Hsiung
发明人： Meng-Hsien Chen , Chung-Yung Ai , Chih-Wei Hsiung
IPC分类号： H01L29/732
CPC分类号： H01L27/10876 , H01L29/66666
摘要： A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.
摘要翻译：制造垂直晶体管的方法包括以下步骤：在衬底中形成多个第一沟槽; 在所述第一沟槽内依次外延生长第一极性层和沟道层，以及在所述沟道层上形成第一延迟层; 沿着与第一沟槽垂直的方向蚀刻第一延迟层和沟道层以形成多个柱; 分别在每个支柱的第一侧壁和第二侧壁上形成栅极; 去除柱上的第一延迟层; 并在柱上外延生长第二极性层。本发明的特征在于使用外延法形成第一极性层，沟道层和第二极性层，并且具有均匀的离子浓度分布的优点。因此，本发明可以制造高质量的垂直晶体管。

2. 发明申请

US20130234230A1 Semiconductor Device and Method for Making the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130234230A1
公开(公告)日：2013-09-12
申请号：US13415959
申请日：2012-03-09
申请人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
发明人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
IPC分类号： H01L27/105 , H01L21/225
CPC分类号： H01L21/2257 , H01L21/2236 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
摘要翻译：半导体器件包括：具有基底和从基底延伸的半导体柱阵列的衬底，衬底形成有多个沟槽，每个沟槽延伸到衬底中并且具有两个相对的沟槽侧壁; 第一绝缘衬垫层，其形成在每个沟槽的每个沟槽侧壁上，并且通过间隙留下每个沟槽侧壁的位形成表面，该间隙未被第一绝缘衬垫层覆盖; 以及多个掩埋位线，每个埋入位线从每个沟槽的相应一个沟槽侧壁的位形成表面延伸到基座中。

3. 发明申请

US20130157454A1 SELF-ALIGNED WET ETCHING PROCESS 有权
标题翻译：自对准湿蚀刻过程
公开(公告)号：US20130157454A1
公开(公告)日：2013-06-20
申请号：US13327157
申请日：2011-12-15
申请人： Wei-Che CHANG , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
发明人： Wei-Che CHANG , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
IPC分类号： H01L21/28
CPC分类号： H01L29/66666 , H01L27/10876
摘要： A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
摘要翻译：自对准湿蚀刻工艺包括以下步骤：在其表面上蚀刻具有蚀刻保护层的衬底，以形成彼此间隔开的多个沟槽; 并且在每个沟槽中依次形成绝缘层，蚀刻停止层和初级绝缘体，其中所述初级绝缘体填充在由所述蚀刻停止层包围的容纳空间的内部。在湿蚀刻工艺期间，蚀刻停止层保护初级绝缘体不被蚀刻，从而实现各向异性湿蚀刻。此外，本发明扩大了与外部电路电连接的接触面积，并且免除了形成在接触区域上的电接触器由于过度蚀刻初级绝缘体而引起的短路。

4. 发明授权

US08461056B1 Self-aligned wet etching process 有权
标题翻译：自对准湿法蚀刻工艺
公开(公告)号：US08461056B1
公开(公告)日：2013-06-11
申请号：US13327157
申请日：2011-12-15
申请人： Wei-Che Chang , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
发明人： Wei-Che Chang , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
IPC分类号： H01L21/302
CPC分类号： H01L29/66666 , H01L27/10876
摘要： A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
摘要翻译：自对准湿蚀刻工艺包括以下步骤：在其表面上蚀刻具有蚀刻保护层的衬底，以形成彼此间隔开的多个沟槽; 并且在每个沟槽中依次形成绝缘层，蚀刻停止层和初级绝缘体，其中所述初级绝缘体填充在由所述蚀刻停止层包围的容纳空间的内部。在湿蚀刻工艺期间，蚀刻停止层保护初级绝缘体不被蚀刻，从而实现各向异性湿蚀刻。此外，本发明扩大了与外部电路电连接的接触面积，并且免除了形成在接触区域上的电接触器由于过度蚀刻初级绝缘体而引起的短路。

5. 发明申请

US20130193511A1 VERTICAL TRANSISTOR STRUCTURE 审中-公开
标题翻译：垂直晶体管结构
公开(公告)号：US20130193511A1
公开(公告)日：2013-08-01
申请号：US13358823
申请日：2012-01-26
申请人： Hsuan-Yu FANG , Wei-Chih Liu , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang , Kazuaki Takesako , Tomohiro Kadoya , Wen Kuei Hsu , Hirotake Fujita , Yukihiro Nagai , Chih-Wei Hsiung , Yoshinori Tanaka
发明人： Hsuan-Yu FANG , Wei-Chih Liu , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang , Kazuaki Takesako , Tomohiro Kadoya , Wen Kuei Hsu , Hirotake Fujita , Yukihiro Nagai , Chih-Wei Hsiung , Yoshinori Tanaka
IPC分类号： H01L27/088
CPC分类号： H01L29/7827 , H01L29/4236 , H01L29/66666
摘要： A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.
摘要翻译：垂直晶体管结构包括基板，形成在基板上并彼此间隔开的多个柱，每个形成在两个相邻柱之间的多个沟槽，形成在第一侧壁的表面上的保护层和沟槽的第二侧壁，分别形成在第一侧壁和第二侧壁的保护层上的第一栅极和第二栅极以及覆盖沟槽底壁的分离层。本发明在蚀刻时使用用作蚀刻停止层的分离层到第一栅极和第二栅极。此外，分离层的厚度用于控制底壁和第一和第二栅极之间的距离，并且通过离子注入限定在柱中形成的漏极和源极的宽度。

6. 发明授权

US08956961B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08956961B2
公开(公告)日：2015-02-17
申请号：US13415959
申请日：2012-03-09
申请人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
发明人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
IPC分类号： H01L21/02
CPC分类号： H01L21/2257 , H01L21/2236 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
摘要翻译：半导体器件包括：具有基底和从基底延伸的半导体柱阵列的衬底，衬底形成有多个沟槽，每个沟槽延伸到衬底中并且具有两个相对的沟槽侧壁; 第一绝缘衬垫层，其形成在每个沟槽的每个沟槽侧壁上，并且通过间隙留下每个沟槽侧壁的位形成表面，该间隙未被第一绝缘衬垫层覆盖; 以及多个掩埋位线，每个埋入位线从每个沟槽的相应一个沟槽侧壁的位形成表面延伸到基座中。

7. 发明申请

US20130230955A1 METHOD FOR FABRICATING A VERTICAL TRANSISTOR 有权
标题翻译：用于制造垂直晶体管的方法
公开(公告)号：US20130230955A1
公开(公告)日：2013-09-05
申请号：US13410102
申请日：2012-03-01
申请人： Meng-Hsien CHEN , Chung-Yung Ai , Chih-Wei Hsiung
发明人： Meng-Hsien CHEN , Chung-Yung Ai , Chih-Wei Hsiung
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L29/66666
摘要： A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.
摘要翻译：制造垂直晶体管的方法包括以下步骤：在衬底中形成多个第一沟槽; 在所述第一沟槽内依次外延生长第一极性层和沟道层，以及在所述沟道层上形成第一延迟层; 沿着与第一沟槽垂直的方向蚀刻第一延迟层和沟道层以形成多个柱; 分别在每个支柱的第一侧壁和第二侧壁上形成栅极; 去除柱上的第一延迟层; 并在柱上外延生长第二极性层。本发明的特征在于使用外延法形成第一极性层，沟道层和第二极性层，并且具有均匀的离子浓度分布的优点。因此，本发明可以制造高质量的垂直晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式